Analysis of the Interface between DDS Chip AD9850 and Single Chip Microcomputer

　　DDS is the abbreviation of Direct Digital Synthesizer. Compared with traditional frequency synthesizers, DDS has the advantages of low cost, low power consumption, high resolution and fast conversion time. It is widely used in the fields of telecommunications and electronic instruments and is a key technology for realizing full digitalization of equipment.

　　With the rapid development of digital technology, the technology of generating multiple frequencies from a reference frequency source by digital control method, namely direct digital frequency synthesis (DDS) technology, has emerged. The highly integrated frequency synthesizer AD9850 launched by AD Company in the United States is one of the typical products using DDS technology.

　　AD9850 adopts advanced CMOS technology, and its power consumption is only 155mW when powered by 3.3V. Its extended industrial temperature range is -40～80℃, and it adopts 28-pin SSOP surface package. The pin arrangement of AD9850 is shown in Figure 1, and Figure 2 is its component block diagram. The middle dotted line in Figure 2 is a complete programmable DDS system, and the outer dotted line contains the main components of AD9850.

　　AD9850 contains a programmable DDS system and a high-speed comparator, which can realize frequency synthesis with full digital programming control. A DDS chip mainly includes three parts: frequency control register, high-speed phase accumulator and sine calculator (such as Q2220). The frequency control register can load and store the frequency control code input by the user in serial or parallel mode; the phase accumulator performs phase accumulation in each clock cycle according to the DDS frequency control code to obtain a phase value; the sine calculator calculates the digital sine wave amplitude for the phase value (the chip is generally obtained by looking up a table). The output of the DDS chip is generally a digitized sine wave, so it needs to pass through a high-speed D/A converter and a low-pass filter to obtain a usable analog frequency signal.

　　The phase register returns to the initial state after every 2N/M external reference clocks, and the phase sine lookup table also returns to the initial position after every cycle, so that the entire DDS system outputs a sine wave. The output sine wave period To = Tc2N/M, frequency fout = Mfc/2N, Tc, fc are the period and frequency of the external reference clock respectively.

　　AD9850 uses a 32-bit phase accumulator to truncate the signal into 14 bits and input it into the sine lookup table. The output of the lookup table is then truncated into 10 bits and input into the DAC, which then outputs two complementary currents. The DAC full-scale output current is adjusted by an external resistor RSET, and the adjustment relationship is ISET=32 (1.148V/RSET). The typical value of RSET is 3.9kΩ. The output of the DAC is low-pass filtered and connected to the high-speed comparator inside the AD9850 to directly output a square wave with very little jitter. The system function is shown in Figure 3.

　　After the AD9850 is connected to a precision clock source and written with a frequency and phase control word, it can generate an analog sine wave output with programmable frequency and phase. This sine wave can be used directly as a frequency signal source or converted into a square wave output by an internal high-speed comparator. Under a 125MHz clock, the 32-bit frequency control word can make the AD9850 output frequency resolution reach 0.0291Hz; it has 5 phase control bits and allows the phase to be adjusted by increments of 180°, 90°, 45°, 22.5°, 11.25° or a combination of these values.

　　2 AD9850 control word and control timing

　　AD9850 has a 40-bit control word, 32 bits for frequency control, 5 bits for phase control. 1 bit for power down control, 2 bits for selecting the working mode. This 40-bit control word can be input to AD9850 in parallel or serial mode. Figure 4 is a control timing diagram for parallel input of the control word. In the parallel loading mode, the data is input to the register through the 8-bit bus A0...D7. After repeating 5 times, the 40-bit data is loaded from the input register to the frequency/phase data register (update the DDS output frequency and phase) at the rising edge of FQ-UD, and the address pointer is reset to the first input register. In the serial input mode, the rising edge of W-CLK serially shifts in one bit of data from pin 25. After shifting 40 bits, the output frequency and phase can be updated with one FQ-UD pulse. [page]

　　The reset (RESET) signal of AD9850 is high level valid, and the pulse width is not less than 5 reference clock cycles. The reference clock frequency of AD9850 is generally much higher than the clock frequency of the microcontroller, so the reset (RESET) terminal of AD9850 can be directly connected to the reset terminal of the microcontroller. Figure 5 is the control timing diagram of the corresponding control word serial input.

　　It is worth mentioning that the two control bits used to select the working mode, whether parallel or serial, are best written as 00. 10, 01 in parallel and 10, 01, 11 in serial are reserved control words for factory testing. Inadvertent use may lead to unpredictable consequences.

　　3 Interface between MCU and AD9850

　　AD9850 has two evaluation boards connected to the parallel printer port of the microcomputer and equipped with software running under Windows, which can be used as an application reference. However, compared with the control implemented by the microcomputer, the control of DDS by the microcontroller has the advantages of simple programming and control, simple interface, low cost, and easy system miniaturization. Therefore, the MCS51 microcontroller is generally used as the control core to send control words to the AD9850.

　　A single-chip microcomputer is a small but complete computer system that is integrated into a circuit chip. It uses ultra-large-scale integrated circuit technology to integrate a central processing unit CPU with data processing capabilities, random access memory RAM, read-only memory ROM, multiple I/O ports and interrupt systems, timers/counters and other functions (may also include display driver circuits, pulse width modulation circuits, analog multiplexers, A/D converters and other circuits) on a silicon chip. A single-chip microcomputer is referred to as a single-chip microcomputer. It is a typical embedded microcontroller (Microcontroller Unit). The English abbreviation MCU is often used to represent a single-chip microcomputer. It was first used in the field of industrial control. The single-chip microcomputer has evolved from a dedicated processor with only a CPU in the chip. The earliest design concept was to make the computer system smaller and easier to integrate into complex control devices with strict volume requirements by integrating a large number of peripherals and CPU into one chip. INTEL's Z80 was the first processor designed according to this idea. Since then, the development of single-chip microcomputers and dedicated processors has gone their separate ways.

　　3.1 I/O mode parallel interface

　　The I/O parallel interface circuit is relatively simple, but it occupies relatively more microcontroller resources. Figure 8 is the circuit diagram of the I/O parallel interface. The data lines D0~D7 of AD9850 are connected to the P1 port, and FQ-UD and W-CLK are connected to P3.0 (pin 10) and P3.1 (pin 11) respectively. All timing relationships can be realized through software control.

　　Store the DDS control word from high to low in 30H to 34H. The program list for sending the control word is as follows:

　　In the program, after each byte of data is sent to the P1 port, P3.1 (W-CLK) must be set high. At its rising edge, AD9850 receives the data on the data line connected to the P1 port, then sets P3.1 low and prepares to send the next byte. After sending 5 bytes continuously, P3.0 (FQ-UD) must be set high again to allow AD9850 to change the frequency and phase output according to the input control word, and then set P3.0 low again to prepare for the next group of transmissions. The P3.0 and P3.1 pins of the microcontroller are serial ports. When they are occupied, the W-CLK and FQ-UD pins can also be connected to other I/O pins. At this time, the corresponding transmission program needs to be modified.

　　3.2 Bus-based parallel interface

　　The bus mode parallel interface occupies less microcontroller resources. In this mode, AD9850 only occupies a section of RAM address as an expansion chip, and can occupy only one address when necessary. Figure 7 is the circuit schematic diagram of the bus mode parallel interface. Similarly, the DDS control word is stored from high to low in 30H to 34H. The program list for sending the control word is as follows:

　　The W-CLK and FQ-UD signals of AD9850 are both effective on the rising edge. When the MOVX @DPTR, A instruction is used to transmit the control word to AD9850, the 74F138 decodes the lower three bits of the upper eight bits of the address, and its output is inverted and ANDed with the inverted signal to obtain a rising edge and sent to the W-CLK pin of AD9850. At this time, the data sent to the bus will be received by AD9850. After sending all the 40-bit control words for five consecutive times, the MOVA A, @DPTR instruction is used to generate the FQ-UD signal to make AD9850 change the output frequency and phase. At this time, the data read into the microcontroller is actually meaningless. The address of AD9850 in Figure 7 is 0700H.

　　The above two interface methods have been proven in practical applications: they work reliably and have good effects. The serial interface between the microcontroller and AD9850 can be designed with reference to relevant materials. The above interface circuit and program are also applicable to AD9851, which is pin-to-pin compatible with AD9850. It is worth noting that the definition of the control word of AD9851 is slightly different from that of the control word of AD9850, which should be paid attention to when programming.