Design of Serial Peripheral Interface SPI Function Module

SPI (Serial Peripheral Interface) is a 3-wire synchronous serial full-duplex communication interface. It has the advantages of simple circuit, high speed and reliable communication. In recent years, a large number of new devices such as LCD modules, FLASH, EEPROM memories, data input and output devices have adopted SPI interface. New microcontrollers generally have SPI interface controllers integrated inside the microcontroller, which can greatly reduce the workload of software.

Since the SPI system bus only needs 3 to 4 data lines and control lines to interface with various I/O devices with SPI bus interface function, and the extended parallel bus requires 8 data lines, 8-16 address lines, and 2 to 3 control lines, the use of SPI bus interface can simplify circuit design, save a lot of interface devices and I/O lines in conventional circuits, improve the reliability of the design, and use the SPI bus to increase the types of application system interface devices and improve the performance of the application system.

2 SPI module interface signals, timing requirements and working modes

2.1 Internal bus interface

In this design, the internal bus interface uses the AMBA bus 3.0 protocol, which has good portability and reusability. SPI is a slave module on the APB bus. The timing of the APB bus fully complies with (ABMA Specification) (Rev 3.0). Therefore, this SPI module supports 3 types of DMA operations. In addition to the standard signal lines, there are 3 interrupt request signal lines connected to the DMA module.

2.2 SPI bus interface and timing

The SPI serial interface uses four lines to directly interface with a variety of standard peripheral devices: serial clock line SCLK, master input/slave output data line MISO, master output/slave input data line MOSI and low-level effective slave select line SSN. SCLK is the master clock line, which provides a synchronous clock signal for the transmission and reception of MISO data.

During normal operation, the 4 pins of the host should be connected to the corresponding 4 pins of the slave respectively.

In order to exchange data with peripherals, the SPI module can configure the polarity and phase of the output serial synchronous clock according to the working requirements of the peripherals. The polarity of the clock (CPOL) has no significant effect on the transmission protocol. If CPOL=0, the idle state of the serial synchronous clock is low; on the contrary, if CPOL=l, the idle state of the serial synchronous clock is high. The clock phase (CPHA) can be configured to select one of two different transmission protocols for data transmission.

If CPHA=0, data is sampled at the first transition edge (rising or falling) of the serial synchronous clock; if CPHA=1, data is sampled at the second transition edge (rising or falling) of the serial synchronous clock. The clock phase and polarity of the SPI master module and the peripherals communicating with it should be consistent. The SPI interface timing is shown in Figures 1 and 2.

Figure 1 CPOL = 0 CPHA = 0

Figure 2 CPOL=0 CPHA=1

2.3 Working Mode

SPI has two working modes, which can be switched by external pin jumpers.

Master mode: Sending and receiving can work in master mode at the same time.

The salient feature of the master mode is that there is always an SCLK signal whether sending or receiving, and the send operation is triggered by writing data to the transmit FIFO. In the master mode, one action of the clock signal corresponds to the transmission of one bit of data (MOSI) and the reception of another bit of data (MISO).

As shown in Figure 3, in the master chip, data is sent from the shift register from right to left to the slave chip (MOSI), and at the same time, the data in the slave chip is sent from left to right to the master chip (MISO), and one byte is sent after 8 clock cycles. The input byte is retained in the shift register, and the SPI INT FLAG bit is automatically set (if an interrupt is set, an interrupt is generated), and the data in the shift register will be latched into the receive FIFO, and the read operation of the receive FIFO will read the data out.

Slave mode: both transmission and reception work in slave mode. The salient feature of slave mode is that both transmission and reception must always be performed under the action of SCLK signal, and SSN signal must be valid.

When the SSN signal is invalid, data transmission cannot be performed and the input data is considered invalid. The data transmission and reception process is shown in Figure 3, which is basically similar to the master mode, except that the data shifting out and input directions of the shift register are opposite.

Figure 3 Master and slave sending and receiving operations

3 SPI module function design

3.1 Module Division

According to the function definition and the working principle of SPI, the entire SPI IP is divided into 8 sub-modules: APB interface module, clock frequency division module, transmit data FIFO module, receive data FIFO module, register control module, command parsing module, interrupt processing module and transmit and receive data module. The entire SPI module division structure diagram is shown in Figure 4.

Figure 4 Data transmission structure

Among these modules, Tx-FIFO and Rx-FIFO are used as FIFOs for receiving and sending data. DMA/INT is an interrupt control module that notifies the MCU or DMA to send or receive data FIFO. CMD ANALYSIS module is used to parse the commands sent by the Host in slave mode. CTRl/Register is used to place registers for MCU to read and write various parameters for configuring SPI. Shifter is used for serial-to-parallel conversion and receiving and sending data. Clock module is used to generate clock in master mode.

3.2 Design

Through in-depth analysis of the four transmission protocols of SPI, it can be found that according to one protocol, as long as the serial synchronous clock is converted, the remaining three protocols can be obtained. In order to simplify the design, it is stipulated that if multiple data are to be transmitted continuously, an idle wait of the serial clock is inserted between two data transmissions, so that the state machine only needs two states (idle and working) to work correctly. Compared with other designs, without basically reducing performance, the idea is more refined and clear, which can greatly shorten the time of writing code and reduce the error rate.

This SPI module has two working modes: query mode and DMA mode. The query mode monitors the SPI status register through the processor core to obtain its status and determine the next action.

The DMA mode controls the data exchange between the memory and the SPI by the DMA module without the participation of the processor core, which effectively improves the bus utilization.

The external MCU can configure the slave mode SPI to a mode that can parse commands by communicating with the internal MCU. In this way, the external master mode SPI can continuously transmit multi-bit data when SSN is low, and the first data on the falling edge is considered as a command. The slave mode SPI can parse these commands and perform corresponding operations. These operations mainly include clearing the data in the receive FIFO or transmit FIFO, selecting MCU or DMA as the object of data interaction, etc., which can greatly save the bandwidth required for interaction with the MCU.

The register control module and SPI core module as the main components adopt synchronous circuit design, and the communication between them adopts asynchronous circuit design. These are mainly considered that the bandwidth of SPI is adjustable through the control of MCU. The clock frequency of the SPI core part is adjustable, which can achieve a variety of bandwidths, increasing the flexibility of the SPI of this design.

3.3 Circuit Implementation

In order to ensure the correctness of the RTL code, the IP functions are fully simulated and verified. The simulation includes RTL-level and gate-level simulation verification. RTL-level simulation is to call the code file into the simulation software of the hardware description language for functional simulation. Gate-level simulation includes simulation before and after layout and routing. Simulation after layout and routing obtains accurate delay parameters. Convert the RTL-level code into a gate-level netlist and a 0.13um process standard cell library.

In the traditional design process, functional verification is first performed by writing test vectors to stimulate the modules that need to be functionally tested, and then observing the output results of the modules to determine whether the functions of the modules are correct. However, when writing test vectors, test engineers perform the tests based on their own understanding of the module functions. This leads to a problem: the stimulus of the module by the test vector may be incomplete or wrong, but the stimulus of the test vector does not reflect the error; it is also possible that the function of the module is correct, and the false alarm error makes the verification process very inefficient. To avoid the above problems, a system-level verification environment is used in the functional verification of this design module. The environment consists of an IP bus, a driver, a monitor, an external module, and a script that coordinates their work. The modules that make up the system can be added to the environment as needed. Each verification process is a process in which the corresponding stimulus acts on the environment. The verification results are generated, verified, and output by the environment. This ensures the completeness and correctness of the test vector.

The verification environment is under the LINUX operating system. The simulator uses Cadence's NC-Verilog and supports C/C++, Verilog and VHDL co-simulation. The SPI module can be directly hung in the verification environment and the software stimulus can be read in through the Verilog $readmemh task for verification.

When the system clock is 36MHz, Figure 5(a) shows the simulation result of sending 6-bit data when CPOL=0 and CPHA=1. Figure 5(b) shows the simulation result of receiving 6-bit data when CPOL=0 and CPHA=0.

Figure 5 Simulation results

These two simulation results show that this design fully supports four SPI transmission protocols and can seamlessly transmit data at the maximum rate.

4 Conclusion

The SPI designed in this paper can be embedded in the SOC chip of the monitoring system as an IP core. The chip has passed the tape-out verification, and all indicators have reached the requirements of the original design. Through board-level testing, the SPI in the chip can support 4 transmission protocols, and the highest working frequency can reach 18M bps. It can capture or echo 15 frames of images in one second, reaching a high level in the industry. The shortcoming of this design is that there is no data verification. With the increase of market demand, CRC verification can be added to the design to increase the correctness of the data and improve system efficiency.