51 MCU interrupt response and cancellation

Interrupt Response

Interrupt response is the acceptance of the interrupt request from the interrupt source by the single-chip CPU. After the interrupt request is responded, it goes through a series of operations and then turns to the interrupt service routine to complete the processing task required by the interrupt. The following briefly describes the interrupt response process of 80c51:

1. External interrupt sampling and internal interrupt setting

1.1 External interrupt sampling

To know whether an external interrupt request occurs, it is necessary to sample the external interrupt.

When the IT0 (or IT1) bit of register TCON is set to 0 by software, /INT0 (or /INT1) is level-triggered, and the CPU samples /INT0 (or /INT1) during S5P2 (fifth state, second beat) of each machine cycle. Once a low level is detected on P3.2 (or P3.3), it is considered that there is an external interrupt request, and the hardware sets the IE0 (or IE1) bit of TCON to 1, requesting an interrupt to the CPU. After the interrupt response is completed, it turns to the interrupt service subroutine, and the hardware automatically clears the IE0 (or IE1) bit to 0.

When the IT0 (or IT1) bit of register TCON is 1 and /INT0 (or /INT1) is in pulse trigger mode, the CPU samples /INT0 (or /INT1) during S5P2 of each machine. When it detects that the previous cycle is high and the next cycle is low, the hardware sets the IE0 (IE1) bit of TCON to 1 and requests an interrupt from the CPU. After the interrupt response is completed and the interrupt service subroutine is turned, the hardware automatically clears the IE0 (IE1) bit to 0. In edge trigger mode, in order to ensure that the CPU detects a negative transition from high to low within two machine cycles, the duration of the high level and the low level must not be less than one machine cycle.

1.2 Internal interrupt setting

80c51 puts all interrupt flags into TCON and SCON registers. External interrupts use sampling to lock interrupt requests on the IE0 (IE1) flag of the TCON register. Since the interrupt requests of timer interrupts and serial interrupts occur inside the chip, timer interrupts can directly set TF0 (TF1) of TCON, and serial interrupts can directly set RI and TI of SCON. There is no sampling problem for internal interrupts.

2. Interrupt query

The so-called query is that the CPU tests the status of each flag bit in TCON and SCON to determine whether an interrupt request occurs and which interrupt request it is. The microcontroller queries the interrupt request flag in the last state (S6) of each machine cycle in order of priority, that is, first query the high-level interrupt and then query the low-level interrupt. The same-level interrupts are queried in the order of "external interrupt 0-timer interrupt 0-external interrupt 1-timer interrupt 1-serial interrupt". If the query finds that a flag bit is "1", it means that an interrupt request occurs, and then the interrupt response starts from the S6 state of the next adjacent machine cycle.

Since interrupt requests occur randomly and the CPU cannot know them in advance, the interrupt query must be repeated in every machine cycle of instruction execution during program execution. In other words, it is like when you are reading a book, you look up every second to listen and see if someone is ringing the doorbell, if there is a phone call, or if the water is boiling. It seems that the microcontroller is much dumber than humans.

3. Interrupt response

When a valid interrupt request is found, the interrupt response is immediately performed. When responding to the interrupt, the hardware automatically generates a long call instruction LCALL XXXX according to the interrupt flags in registers TCON and SCON. Here, XXXX is the entry address of the corresponding interrupt in the interrupt area of ​​the program memory. For the five independent interrupt sources of 80c51, these entry addresses have been set by the system. In this way, after the corresponding interrupt is generated, it can be transferred to the corresponding location for execution.

For example, in response to external interrupt 0, the long call instruction generated is

LCALL 0003H

After the LCALL instruction is generated, it is immediately executed by the CPU. First, the content of the current program counter PC (the address of the instruction to be executed) is pushed into the stack to protect the breakpoint, and then the interrupt entry address is loaded into the PC, so that the program is redirected to the corresponding interrupt area entry address. From the vector address corresponding to the interrupt source, it can be seen that there are only 8 units between an interrupt vector entry address and the next interrupt vector entry address. In other words, if the length of the interrupt service program exceeds 8B, it will occupy the entry address of the next interrupt, resulting in an error. But in general, it is rare for an interrupt service program to occupy less than 8B. For this reason, you can write an "LJMP XXXX" or "AJMP XXXX" instruction at the interrupt entry, so that the program that actually handles the interrupt can be placed in any position in the ROM.

For example, if external interrupt 0 is used, the following can be written at the beginning of the program:

ORG 0000H

LJMP MAIN

ORG 0003H

LJMP INT_0

; The following is the main program

MAIN:

; The following is the external interrupt 0 service program

INT_0:

RETI

END

After the interrupt service program is completed, a RETI instruction must be executed. After executing this instruction, the CPU will take out the address saved in the stack and send it back to the PC, then the program will continue to execute from the interrupt point of the main program.

Description The protection work done by the CPU is very limited. It only protects one address (the address where the main program is interrupted), and all other things are not protected. Therefore, if you use A, DPTR, PSW, etc. in the main program, and want to use them in the interrupt program, you must ensure that after returning to the main program, the data in the data is still the data before the interrupt, so you have to protect it yourself.

The CPU reads the interrupt flag at the S5P2 stage of the machine cycle and checks it in the next machine cycle. If the interrupt condition is met, the system will automatically generate a LCALL to the corresponding interrupt service routine. However, if there are any of the following three situations, the system will not respond to the interrupt request signal:

a An equal or higher level interrupt is being executed. This is the same as handling an emergency. Since the emergency is being handled, no other interrupt conditions will be accepted unless the next interrupt situation has a higher priority.

From this we can get a concept: all interrupt programs should be as simple as possible, and return to the main program immediately after handling the interrupt, so as not to take up too much time and affect the performance of the system.

b The current machine cycle is not the last cycle of the instruction. Since the 80c51 has 1, 2, and 4 machine cycles when executing instructions, the system will respond to the interrupt signal only after the instruction is completely executed. For example, when the system is executing the MUL AB instruction (which takes 4 machine cycles), the interrupt signal must appear on the 4th machine cycle to be effective. This means that the interrupt signal must last long enough so that the 80c51 CPU has time to respond.

cIf the instruction being executed is RETI or an instruction about interrupt setting IE and IP, it will not respond to the interrupt signal that happens to appear, because the above situation happens to be the end of an interrupt service program, or an instruction to allow/disable an interrupt. Of course, it will respond to the interrupt signal only after these instructions are executed. These instructions take up to two machine cycles, so the interrupt signal at this time must be maintained for more than two machine cycles to be accepted by 80c51.

Removal of interruption

After the interrupt response, the interrupt request flag in TCON or SCON should be cleared in time. Otherwise, it means that the interrupt request still exists, which may cause repeated query and response of the interrupt, so there is a problem of removing the interrupt request.

1 Timer interrupt request cancellation

After the timer interrupt is responded, the hardware automatically clears the flag bit TF0 (or TF1) to 0, so the interrupt request of the timer interrupt is automatically removed without user intervention.

2 Serial interrupt software cancel

For serial interrupts, after the CPU responds to the interrupt, its interrupt flags RI and TI are not cleared by hardware. They must be cleared by software in the interrupt service routine to cancel the interrupt request.

3. Cancellation of external interrupt request

The removal of external interrupts includes clearing the interrupt flag IE0 (or IE1) to 0 and removing the external interrupt request signal. IE0 (or IE1) is cleared to "0" by the hardware circuit automatically after the interrupt response. The only thing left is the removal of the external interrupt pin request signal. The following discusses the two triggering methods, pulse and level.

aFor pulse interrupt requests, since the pulse signal disappears after a while, it can also be said that the interrupt request signal is automatically removed.

b. For level-mode external interrupts, the interrupt flag is automatically removed, but the low level of the interrupt request signal may continue to exist. When the machine cycle is sampled in the future, the IE0 or IE1 flag bit that has been cleared to 0 will be reset to 1. Therefore, in order to completely solve the removal of level-mode external interrupts, in addition to clearing the flag bit to 0, if necessary, the interrupt request signal pin must be forced to change from a low level to a high level after the interrupt response. To this end, a circuit as shown in the figure can be added to the system

External interrupt request flag removal circuit

As can be seen from the figure, the external interrupt 0 request signal is at the clock input end of the D flip-flop (74LS74 can be used). When an interrupt request signal (low level) appears from an external device, the Q end outputs a low level, /INT0 is valid, and an interrupt request signal is sent to the CPU. After the CPU responds to the interrupt, the software arranges a low-level interrupt response signal in the interrupt service program, which is sent from P1.0 to the /SD (set end, low level is valid) of the D flip-flop, making the Q end of the D flip-flop output a high level, thereby removing the low-level external interrupt 0 request signal. The low level required by the /SD end can be obtained by adding the following instructions in the interrupt service program:

ANL P1,#0FEH ; Make P1.0 output low level, D flip-flop set

In the interrupt service program, the instruction to remove the interrupt flag except 0 must be added, that is,

CLR IE0; Clear the external interrupt flag so that it can interrupt again next time

It can be seen that the removal of the level-mode external interrupt request signal is achieved through a combination of software and hardware.