Design of Ethernet Interface in PowerPC Embedded System

      The PowerPC was designed in 1993 by a coalition of IBM, Apple, and Motorola (whose semiconductor division is now spun off as Freescale).

      PowerPC technology is based on RISC (Reduced Instruction Set Computer), which is derived from IBM's POWER (Performance Optimized Enhanced RISC) architecture. PowerPC chips are mainly used in embedded systems because of their high performance and low power consumption. MPC7410 is a new generation of G4 processor. By adding AltiVec technology, the processing power reaches 4G FLOPS, and the low voltage operation of 1.8 V greatly reduces the power consumption of the chip and improves the stability of the system. The internal main frequency of MPC7410 is up to 500 MHz, and each clock cycle can execute up to 8 instructions, including 4 vector operation (AltiVec) instructions and 2 integer instructions. The system uses MPC7410 as the core processor to build an embedded system hardware platform. The PCI interface of the Tsi107 chipset is used to connect to Ethernet. The network port is a very important communication interface of the system. Usually, the download of the operating system image and communication with the outside world are carried out through the Ethernet port. This paper introduces the Ethernet interface hardware design and the development of VxWorks BSP.

      2 System Architecture Overview

      The whole system structure block diagram is shown in Figure 1.

      The system uses Motorola's RISC processor PowerPC7410 as the core processor, which has the characteristics of high performance and low power consumption. It is connected to a 2 MB L2 as a secondary cache to improve the operation speed. The bridge chip/memory controller Tsi107 designed by Tundra for PowerPC is used as the north bridge chip. The 60X bus is connected to MPC7410 to convert the 60X bus signal into PCI bus signal and manage FLASH and SDRAM. This design makes full use of the high data transmission rate and excellent connection performance of the 60X bus, and gives full play to the high reliability and powerful processing ability of MPC7410, so that the hardware platform has high performance.

      3 PCI interface of Tsi107

      The PCI interface of Tsi107 is compatible with the PCI 2.1 specification. It uses a 32-bit address/data multiplexed line. It provides internal buffering between the PCI bus and the processor or local memory. The processor has 1 32 B buffer for read and write operations respectively, and the memory operation has 2 32 B read buffers and 2 32 B write buffers. The PCI bus uses a central arbitration method, and each master has its own request ( ) and obtain ( ) signals. Control of the bus can be obtained through a simple request-acquire handshake. Arbitration occurs during the previous access, so it does not occupy PCI bus cycles.

      Tsi107 provides bus arbitration logic for itself and up to 5 other PCI bus masters. You can decide whether to enable (set to 1) or disable (set to 0) the on-chip PCI arbiter by setting bit 15 of the PCI arbitration control register (PACR). When the reset signal ( ) is high, collect SDMA9 to determine whether the on-chip PCI arbiter is enabled (low) or disabled (high).

      The on-chip PCI arbiter uses a programmable, two-level, round-robin arbitration arithmetic logic. Each of the five external masters, plus Tsi107, is programmed into two priorities, high or low, using the appropriate bits in the PACR. The low priority group shares a bus request transmission channel in the high priority group. If there are N high priority devices and M low priority devices in the system, each high priority device will get at least one bus transmission, and each low priority device will get at least one bus transmission.

      4 Address Mapping

      According to the role of Tsi107 in the circuit, its working mode can be divided into two types, host mode and agent mode. In host mode, PowerPC is the main CPU of the entire board, and Tsi107 manages the memory and PCI bus of the entire system. In agent mode, the PowerPC system is a PCI device, and Tsi107 is responsible for communicating with the PCI host bridge and managing the local memory of this PCI device. The entire PowerPC system is managed by the PCI host bridge. In this system, Tsi107 works in host mode. Tsi107 can use two address mapping modes in host mode, map A and map B. The address mapping mode is selected by the address mapping configuration pin SDBA0 at reset. If Tsi107 works in host mode and SDBA0 is pulled up, Tsi107 uses map B. It is recommended not to use map A. When using map B, the address mapping relationship between PowerPC and PCI is shown in Table 1.

      5. Network port design

      The design of the network port is based on the PCI bus controlled by the chipset Tsi107. The basic block diagram is shown in Figure 2.

      The network port is mainly composed of Intel 82559, network isolation transformer and RJ4S interface. 82559 is a highly integrated, high-performance, low-power 10/100 Mb/s Fast Ethernet controller that complies with LON design specifications. The physical size is only 15 mm×15 mm, making it a cost-effective chip. 82559 has a complete PCI interface and can be used as both a master device and a slave device. It can only be used as a slave device when the system is powered on and configured, and can be used as a master device after normal operation. The 32-bit PCI controller enables 82559 to perform high-speed data transmission on the PCI bus. And the PCI controller can handle communication tasks, thereby reducing the burden on the CPU. 82559 contains a transmit FIFO and a receive FIFO, each of which is 3 kB in size, which can prevent data loss while waiting for bus transmission. This will enable 82559 to transmit data using the minimum frame spacing. 82559 can operate in full-duplex and half-duplex modes. 82559 is connected to an E2PROM, which provides power-on initialization for hardware and software. The 82559 chip integrates the functions of MAC (media access sublayer) and PHY (physical layer), and communicates with PowerPC via the PCI bus through the on-chip command and status registers. H1102 is a network isolation transformer. 82559 drives the RJ45 network cable interface through the network isolation transformer to support 10/100BASE-T and realize communication with the outside world. [page]

      6 Development of VxWorks BSP for Ethernet

      BSP stands for Board Support Package, which is the underlying support software for the target system. For a specific hardware platform, all hardware-related codes are encapsulated in the BSP, which provides a virtual hardware platform to the upper layer. The BSP interacts with the operating system through a defined interface. BSP is a collection of all hardware-related code bodies, and is a layer between the underlying hardware and the upper operating system. Its main purpose is to support the operating system so that it can run better on the hardware system. The following introduces the development method of the VxWorks BSP for the network port.

      6.1 Register initialization of the PCI interface of Tsi107

      The register initialization of the PCI interface of Tsi107 mainly involves the setting of PCI command register, PCI status register, PCI arbitration control register and other PCI-related registers. Since the parameters of each register are described in detail in the user manual, they will not be repeated here.

      The address of the 32-bit configuration register in Tsi107 is 0x8000_00nn, where nn is the relative offset address of the register. The configuration register is accessed indirectly. The address of the configuration register is written to the CONFIG_ADDR port, and the content of the configuration register is obtained at the CONFIG_DATA port. The address of the CONFIG_ADDR port is: 0xFEC0_0000~0xFEDF_FFFC, and the address of the CONFIG_DATA port is 0xFEE0_0000~0xFEEF_FFFF.

      6.2 Register initialization of 82559 PCI interface

      The register initialization of the PCI interface of Tsi107 includes the setting of the PCI command register, PCI status register, cache line size (CLS) register and other registers, so as to find the PCI device 82559 and enable the PowerPC to access the device.

      PCI defines three address spaces: PCI memory space, PCI I/O space and PCI configuration space. PCI memory space and PCI I/O space use direct access. PCI supports two types of configuration access, type 0 and type 1. The AD[31:0] signal uses different forms according to the type of configuration access when representing the address. The lower two bits of the address indicate the type of configuration access - type 0 (AD[1:0]=0b00) or type 1 (AD[1:0]=0b01). Both address forms indicate a specific device and a specific configuration register of the device. Type 0 is used to select a device on the local PCI bus, and type 1 transmits the configuration request to another PCI bus through a PCI-to-PCI bridge. The system uses type 0 configuration, as shown in Figure 3.

      To access the configuration space, a 32-bit value must be written to the CONFIG_ADDR register, which defines the target PCI bus, the target device on the bus, and the configuration register to be accessed in the device. A read or write operation to the CONFIG_DATA register will cause the host bridge to convert the access into a PCI configuration cycle (the enable bit in CONFIG_ADDR is set and the device number is not Ob1_1111).

      For map B, the processor can access the CONFIG_ADDR register using any address in the address space 0xFEC0_0000 to 0xFEDF_FFFF. Although the system can use any address in 0xFEC0_0000 to 0xFEDF_FFFF, the address 0xFEC0_0CF8 is generally used. For simplicity, the address of CONFIG_ADDR is usually referred to as CF8. The processor can access the CONFIG_DATA register at any address in the address space 0xFEE0_0000 to 0xFEEF_FFFF. The most commonly used addresses are 0xFEE0_0CFC to 0xFEE0_0CFF. For simplicity, it is generally referred to as CFC.

      For type 0 configuration, Tsi107 converts the device number of the CONFIG_ADDR register into a unique IDSEL signal, and there is a one-to-one correspondence between them. The function number and register number will be copied to AD[10:2] without change, and AD[1:0] is 0b00 in type 0 configuration.

      6.3 Interrupt Implementation

      The EPIC (Programmable Interrupt Control Unit) of Tsi107 supports 5 external interrupts. The IRQ[0:4] signals represent external interrupts, which are controlled and initialized by 5 IRQ vector/priority registers (IVPR0-IVPR4). External interrupts can be set to level or edge triggered. The software sets the priority for each interrupt source by writing to the vector/priority register. The priority value is between 0 and 15, with 15 being the highest. The EPIC unit requests an interrupt from the processor core through INT. When the processor responds to the interrupt request by reading the interrupt response register (IACK) in the EPIC unit, the EPIC returns an 8-bit interrupt vector to the processor, and then the processor handles the interrupt. When the processor writes to the end interrupt (EOI) register of the EPIC unit, the interrupt processing is completed.

      The initialization of EPIC mainly sets the priority of each interrupt source and the interrupt vector, including the setting of the feature report register (FRR), global configuration register (GCR), pseudo vector register (SVR), external and internal interrupt registers, etc.

      7 Conclusion

      Build an embedded system hardware platform with MPC7410 as the core processor, explain the Ethernet interface hardware design and VxWorks BSP design method, so that the Ethernet interface can communicate normally in the system.