Design of I2C bus software module based on C language

 1 I2C Bus Overview

　　I2C (Intel-Integrated Circuit) bus is an inter-chip serial bus expansion technology introduced by Philips in the Netherlands in the early 1980s. It uses two lines (data line SDA, clock line SCL) to complete full-duplex synchronous data transmission between the host and the device on the bus, and can easily form a multi-host system and peripheral device expansion system. The I2C bus supports all devices manufactured by NMOS, CMOS, TTL and other processes, and all nodes on it are connected to the SDA and SCL of the same name. The I2C general method and data transmission have the same operation mode, the interface electrical characteristics are the same and independent, and the IC chip can be removed or added from the system when the system is powered. Peripheral devices with I2C interface have response capabilities, and there is an automatic address increase function when reading and writing on-chip units, which makes it easy to realize automatic operation of multiple bytes. In recent years, international companies have manufactured hundreds of I2C bus devices, such as 8051 series microcontroller 8XC752, LCD driver, RAM, I/O interface and other chips all use I2C bus interface. With the development of digital technology, I2C bus control systems have been applied to more and more electronic products.

2 Data transmission of I2C bus

2.1 Interface Characteristics

The data line SDA and clock line SCL of the I2C bus interface must be connected to the positive power supply VDD through a pull-up resistor. The output end of each I2C interface circuit must be an open drain or an open collector in order to complete the "wired AND" function. The SDA and SCL of I2C are both bidirectional transmission lines. When the bus is idle, both lines are "1" (high level). Since different devices are connected to the I2C bus, the signal levels of logic "0" (low) and "1" (high) depend on the voltage of VDD. The maximum number of devices that can be connected to the bus depends on its capacitance tolerance of 400PF.

2.2 Transmission Timing on the I2C Bus

Each bit of data transmitted on the I2C bus corresponds to a clock pulse. In standard mode, it can reach 100 kbit/s, and in high-speed mode, it can reach 400 kbit/s. A simple master/slave relationship (master/slave) can be established on the bus according to the different functions of the devices. Only devices with CPU can become the master controller. Figure 1 shows a complete data transmission on the I2C bus. During the period when SCL is high, the state of SDA must be stable, and the state of SDA is allowed to change only when SCL is low. During the period when SCL remains high, a high-to-low transition of SDA will start the I2C bus, and a low-to-high transition will stop data transmission. The start and stop signals are usually generated by the master controller. The signal timing of the I2C bus is strictly regulated. This application adopts the standard mode, with an SCL low-level period of ≥4.7μs, an SCL high-level period of ≥4.0μs, and a bus idle time between START and STOP of ≥4.7μs. Each byte transmitted on the I2C bus must be 8 bits, and the number of data bytes that can be transmitted between start and stop is not limited. Serial transmission is adopted, and the highest bit is transmitted first. Each byte must be followed by an acknowledge bit. During the period when the master controller generates the clock pulse required for the response, the transmitter must release the data line (SDA is high) so that the receiver can output the acknowledge bit. A low level is an acknowledge signal, and a high level is a non-acknowledge signal. The non-acknowledgement signal is when the master controller acts as a receiver. After receiving the last byte of data, it must send a non-acknowledgement signal to the controlled transmitter, so that the controlled transmitter releases the data line so that the master controller can send a stop signal to terminate the data transmission. The non-acknowledgement signal will also appear when the slave device can no longer receive bytes. The devices on the I2C bus generally have two addresses: the controlled address and the general broadcast access address. Each device has a unique controlled address for fixed-point communication, and the same general broadcast access address is used by the master to access all devices at the same time. As shown in Figure 1, the first byte sent by the master controller after the start signal is the controlled address of the device being read, which is called the addressing byte. The addressing byte consists of the high 7-bit address and the lowest 1-bit direction bit. The direction bit is "0" indicating that the master controller writes to the controlled device (W), and the direction bit is "1" indicating a read operation (R) on the controlled device. After the start signal, each device on the bus compares its address with the first 7 bits of the addressing byte. If they are the same, the device is selected, generates a response, and decides whether to receive or send in data transmission based on the read and write bits. Whether it is the master sender, master receiver or slave sender, slave receiver, it is controlled by the master device. After the data is transmitted, the master controller must send a stop signal .

　　C51 language is a high-level programming language developed for Intel's 8-bit single-chip microcomputer MCS-51 series, with the characteristics of general C language. Since 1985, many companies have launched C language compilers for the 51 series, among which Franklin C51 compiler is relatively advanced in code generation. It can generate the least code, support floating point and long integer, reentrancy and recursion. The header file reg51.h contains the byte definition and bit definition of the special function register (SFR) of the 51 single-chip microcomputer. In order to be compatible with the 51 single-chip microcomputer with I2C bus interface, P1.6 and P1.7 of the single-chip microcomputer can be defined as the SCL and SDA signals of the I2C bus at the beginning of the program. In practice, other I/O pins can also be used as SCL and SDA signals. In C51 language, as long as the assignment statement "=" is used, the data output and reading of a certain bit of the I/O port can be realized. The I2C bus bottom read and write function interface and functions are listed below. It can be used for 51 series microcontrollers without internal I2C interface to communicate with I2C bus devices. [page]
#include＜reg51．h＞

/*Global symbol definition*/

＃define HIGH1

＃define LOW 0

＃define FALSE0

＃define TRUE1

＃define time 1
＃define uchar unsigned char　　

＃define uint unsigned int

sbit SCL＝P1＾6；

nice SDA＝P1＾7；

1) Function prototype: void delay (uchar nu m)　
Function: Use for () loop to provide delay. In actual application, the input parameters can be changed according to the specific situation, but the requirements of SCL high and low level cycle in I2C bus timing must be met. In this application, 1 is taken and the calling form is delay (time).

2) Function prototype: void start (void)　
Function: Provide the start bit in the I2C bus working timing. During SCL = HIGH, SDA changes from high to low. Before returning, pull SCL low to allow data changes and prepare for transmission. In which function 1 is called.

3) Function prototype: void stop (void)　
Function: The function provides the start bit in the I2C bus working timing. During SCL = HIGH, SDA changes from low to high. In which function 1 is called.

4) Function prototype: void sendbyte (uchar b, uchar * error)　
Function: Under the action of the clock, the 8-bit data in the input parameter b is sent from high to low through the SDA line, and the response signal is read back and stored in the pointer variable * error. Functions 1, 2, and 3 are called.

5) Function prototype: void readbyte (uchar * b, bit Ack)　
Function: The function receives 8 bits of data under the action of the clock and stores it in * b. The first bit received is the high bit, and a response signal (Ack = 0) is sent. When the last byte is received, a non-response (Ack = 1) is sent. Functions 1, 2, and 3 are called.

6) Function prototype: void send-n-byte (uchar * info, uint n, uchar address, uchar * fault) Function: Send n data bytes to the I2C device continuously. The data is stored in the array info［］. Address is the device controlled address. The last bit is 0 (write). The address of n data can be sent as a data byte, or the address automatic addition and subtraction function can be set. * fault stores the received response bit. Functions 1-4 are called.

7) Function prototype: void receive＿n＿byte（uchar＊info，uint n，uchar address，uchar＊fault）　
Function: Receive n bytes of data from I2C device continuously and store them in the array info［］. Address is the device address. This function ensures that the last bit of the device address is 1 (read). The device address of n data can be sent as data bytes, or the automatic addition and subtraction function of the address can be set. Send a non-response signal 1 when receiving the last byte. ＊fault stores the received response bit. Functions 1-5 are called. The

following only takes the sendbyte() function prototype as an example to illustrate how C51 implements the sending of I2C bus:
void sendbyte（uchar b，uchar＊error）

｛int count；
bit data＿bit；

＊error＝0；
for（count＝7；count＞＝0；count－－）

{data_bit＝（bit）（b＆0x80）；
b＝b＜＜1；
／＊Send data bit, generate clock pulse＊／

SDA＝data＿bit；
SCL＝LOW；delay（time）；

SCL＝HIGH；delay（time）；

SCL＝LOW；delay（time）；
｝
／＊Release the data line, generate clock pulse, read back the response＊／

SDA＝HIGH；

SCL＝LOW；delay（time）；

SCL＝HIGH；delay（time）；

*error＝（uchar）SDA；
//Release the data line and set the clock low＊／

SDA＝HIGH；
SCL＝LOW；delay（time）；｝[page]

4 I2C bus for HDTV digital terrestrial receiver

　　Digital high-definition television (HDTV) is the third generation of television system after black-and-white television and color television. Compared with the televisions currently on the market, its image quality (resolution) in both horizontal and vertical directions has been more than doubled. When using a large-screen display or watching at close range, its image is delicate and lifelike, without flickering or roughness, and its quality is comparable to that of 35mm movies. Coupled with digital surround sound, the viewing effect is greatly improved. All HDTV programs are produced, sent and received in digital mode, making the image quality close to that of a studio. At the same time, the digital television system can also provide a variety of services, realizing functions such as interaction, data broadcasting and computer networking. The United States took the lead in officially broadcasting digital HDTV signals in November 1998. my country launched the research and development project of HDTV functional prototype system, a major national industrial project, in 1996, and successfully carried out digital television trial broadcasts during the 50th anniversary of the National Day.

　　This HDTV digital terrestrial receiving system is based on the European DVB-T (Digital Video Broadcasting Terrestrial) standard, completes channel demodulation and decoding, and outputs standard MPEG-2 code streams. Due to the use of COFDM (Coded Orthogonal Frequency Division Multi-plexing) coded orthogonal frequency division multiplexing technology, it can effectively resist multi-path propagation and co-channel interference. The main feature of this receiver is that it uses the L64 series chip with an I2C bus interface. AT89C52 completes the read and write operations and monitoring of the registers in the L64 chip through the I2C bus, and cooperates with the PC to realize the debugging functions based on parameter configuration, mode conversion, and status reading. The structure is simple and debugging is convenient. The basic hardware composition of channel demodulation and decoding is shown in Figure 2 (the pull-up resistor is not drawn). The L64 series of LSILogic Company in the United States is a dedicated demodulation and decoding chip based on the DVB standard. The series is internally modularized, the interface is standardized, and it has an I2C bus interface, which is simple to connect. The L64 series has complete functions. L64780, L64724, and L64768 can be used alone to complete the entire process of DVB standard terrestrial, satellite, and cable TV signal demodulation. At present, the L64 series can be used in combination. As shown in Figure 2, the signal from the channel is first converted into an intermediate frequency signal by the tuner, and then sent to L64780 to complete the main OFDM demodulation. Its output is decoded by L64724 Viterbi and L64768 RS to complete forward error correction and output a standard MPEG-2 code stream. The following only takes L64768 as an example to introduce the C51 function prototype and main functions of reading and writing a register: Define the controlled address of 768: #define LSI0xfe Function prototype: uchar general_call (void) Function: general_call() function calls send_n_byte() function, sends special addressing bytes 0x00 and 0x06, returns 0 if the response is zero, otherwise repeats the previous operation, and returns 1 if there is still no response after sending 5 times. This function is called when the main program is initialized, and the main program returns accordingly. Function prototype: uchar 768＿fec＿rd（uint group，uint addr，uint＊data）Function: 768＿fec＿rd() function calls send＿n＿byte() and receive＿n＿byte(), reads a byte of data from the FEC register and stores it in the pointer variable ＊data, group is the group number, the input group number should be translated into the corresponding group address group＿addr, addr is the FEC register address, and LSI is the addressing byte after each start signal. According to the transmission timing of 768, the low byte of addr is sent first, then the high byte of addr is sent, and then group＿addr is sent, and the data in the corresponding register can be read. If the group number is wrong, 1 is returned; if a non-response signal is received, 0 is returned; if the reading is correct, 2 is returned. The main program performs corresponding operations according to the return value.

5 Conclusion

　　As broadcasting and television technology rapidly moves toward the digital age, it is possible for HDTV to gradually enter the market worldwide in the next five years. I2C bus technology is applied to HDTV digital terrestrial receivers, and an 8-bit single-chip microcomputer is used to control the state of the receiver, which not only reduces the number of buses and improves reliability, but also greatly reduces costs. In actual use, a keyboard, display circuit and corresponding program can be added, or a PC can be used to communicate with the single-chip microcomputer through the RS232 port for debugging. This application has been used in the research and development project of HDTV functional prototype system in my country.