STM32-IWDG independent watchdog use

STM32---Use of IWDG independent watchdog

The independent watchdog (IWDG) is driven by a dedicated 40kHz low-speed clock.

It still works even if the master clock fails.

The window watchdog is driven by the clock obtained by dividing the APB1 clock.

Detect unusually late or early operation of an application through a configurable time window.

IWDG is best suited for applications that require a watchdog as a

Able to work completely independently and in situations where low time accuracy requirements are required.

WWDG is best suited for applications that require the watchdog to function within a precise timing window.

IWDG main performance

●Free running down counter

● Clock provided by independent RC oscillator (can work in stop and standby modes)

●After the watchdog is activated, a reset occurs when the counter counts to 0x000

Write 0xCCCC in the key register (IWDG_KR) to start enabling the independent watchdog;

At this point the counter starts counting down from its reset value 0xFFF.

When the counter counts to the end 0x000, a reset signal (IWDG_RESET) is generated.

Whenever 0xAAAA is written to the key register IWDG_KR,

The value in IWDG_RLR will be reloaded into the counter to avoid a watchdog reset.

If the user enables the "Hardware Watchdog" function in the option byte,

After the system is powered on and reset, the watchdog will automatically start running;

If the software does not write the corresponding value to the key register before the counter ends,

The system will reset the register access protection

The IWDG_PR and IWDG_RLR registers have a write protection function.

To modify the values ​​of these two registers, you must first write 0x5555 to the IWDG_KR register.

Writing to this register with a different value will disrupt the order of operations and the register will be protected again.

A reload operation (ie writing 0xAAAA) will also activate the write protection function.

The status register indicates whether the prescaler value and the down counter are being updated.

//Start independent watchdog

IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable); //Enable register write before access

IWDG_SetPrescaler(IWDG_Prescaler_64); //64 division, one cycle 1.6ms

IWDG_SetReload(800); //Longest 12 bits [0,4096] 800*1.6=1.28S

/* Reload IWDG counter */

IWDG_ReloadCounter();

IWDG_Enable();// Enable IWDG (the LSI oscillator will be enabled by hardware)

Because the independent watchdog uses LSI, it is best to make the clock source stable when the program starts:

/* Start LSI */

RCC_LSICmd(ENABLE); //Open LSI

while(RCC_GetFlagStatus(RCC_FLAG_LSIRDY)==RESET);//Wait until LSI is stable