The relationship between the ARM processor CPSR flag and the conditional

The purpose of this article is to clarify the relationship between the CPSR status flags of the ARM processor and the conditional symbols of the ARM instructions.

1. CPSR Register

The bit allocation in the CPSR register of ARM V4 (and the SPSR register that stores it) is shown in Figure 1 below.

Figure 1 Program Status Register Format

The meaning of the status flag bit: (The meaning of other bits is irrelevant to the topic of this article and will not be introduced here)

N

N=1 means the result of the operation is a negative number; N=0 means the result of the operation is a positive number or zero;

WITH

Z=1 means the result of the operation is zero; Z=0 means the result of the operation is non-zero;

C

There are 4 ways to set the value of C:

─ Addition operation (including comparison instruction CMN): When the operation result produces a carry (unsigned number overflow), C=1, otherwise C=0.

─ Subtraction operation (including comparison instruction CMP): When a borrow occurs during the operation, C=0, otherwise C=1.

─ For non-addition/subtraction instructions that include shift operations, C is the last bit of the value shifted out.

─ For other non-addition/subtraction operation instructions, the value of C usually does not change.

V

There are two ways to set the value of V:

─ For addition/subtraction instructions, when the operands and the operation results are signed numbers represented by binary's complement, V=1 indicates sign bit overflow.

─ For other non-addition/subtraction operation instructions, the value of V usually does not change

2. Conditional symbols and corresponding flags

Table 1 Conditional character description table

3. More explanations about C and V values

The processor uses two's complement to represent signed numbers. The integer range that can be expressed by 8 binary bits is: +127 ~ -128, and the range of 16 bits is: +32767 ~ -32768. If the result of the operation exceeds this range, an overflow occurs. If there is an overflow, it means that the result of the operation of the signed number needs to consider the overflow.

The overflow flag V and the carry flag C are two flags with different meanings. The carry flag indicates whether the result of an unsigned number operation is out of range; the overflow flag indicates whether the result of a signed number operation is out of range.

When the processor operates on two operands, it obtains the result according to the unsigned number and sets the carry flag C accordingly; at the same time, it sets the overflow flag V according to whether it exceeds the range of the signed number. [page]

It is up to the programmer to decide which flag to use. That is, if the operands involved in the operation are considered to be unsigned numbers, then the carry should be taken into account; if they are considered to be signed numbers, then the overflow should be taken into account.

There is a simple rule to determine whether the result of an operation overflows: overflow occurs only when two numbers with the same sign are added and the sign of the result of the operation is opposite to the sign of the original data; in other cases, overflow will not occur.

Code example 1:

LDR     r0, =0x7fffffff

LDR     r1, =0x70000000;

ADDS r0, r0, r1; //result = 0xefffffff

For unsigned arithmetic, there is no carry.

For signed arithmetic, overflow occurs.

At this time, C=0 V=1;

Code example 2:

LDR     r0, =0xffffffff

LDR     r1, =0x70000000;

ADDS r0, r0, r1; //result = 0x6fffffff

For unsigned number operations, there is a carry.

For signed arithmetic, there is no overflow.

At this time, C=1 V=0;

Code example 3:

LDR     r0, =0x8fffffff

LDR     r1, =0xf0000000 ;

ADDS r0, r0, r1; //result = 0x7fffffff

At this time, C=? V=?; (Think about it, and then verify it in the ARM simulator)

Code Example 4: // Thinking about the impact of C value when subtracting

LDR     r0, =0x3

LDR     r1, =0x2

SUBS    r0, r0, r1

contrast:

LDR     r0, =0x3

LDR r1, =-2; (-2's complement 0xfffffffe will be sent to r1)

ADDS    r0, r0, r1

4. The relationship between the CPSR status flag and the conditional symbol of the ARM instruction

With the above background knowledge, let's think about the relationship between the CPSR status flags and the conditional symbols of the ARM instructions in Table 1. Let's select one of them for analysis.

For example: GE: (signed number greater than or equal to)

N=0 V=0: The result is a number greater than or equal to 0, and there is no overflow, so the greater than or equal relationship holds.

N=1 V=1: The result is less than 0, but there is a signed overflow

Consider the following case: c = ab

1.a<0, b<0

Signed overflow is not possible during subtraction

2.a>0, b<0

It is possible that N=V=1? For example (8 digits): 100-(-100)=200

Obviously a>b

3.a<0, b>0

Referring to the simple rules for judging the overflow flag mentioned above, it can be concluded that: in this case,

If the result of a subtraction operation is less than 0 (N=1), no signed overflow will occur.

Therefore (under the premise of N=1 V=1 a<0,b>0) this situation cannot occur

4.a>0, b>0

Signed overflow is not possible in a subtraction operation.

The analysis process for other items is similar.

V. Conclusion

Although the above analysis may seem a bit complicated, in most cases a simple conditional test instruction is sufficient, and the programmer does not need to calculate the exact value of the condition code to get the desired result.