ARM9 series processors—embedded processors

The new generation of ARM9 processors, through a new design, use more transistors and can achieve more than twice the processing power of ARM7 processors. This increase in processing power is achieved by increasing the clock frequency and reducing the instruction execution cycle.

1. Increase of clock frequency

The ARM7 processor uses a 3-stage pipeline, while the ARM9 uses a 5-stage pipeline. The added pipeline design improves the clock frequency and parallel processing capabilities. The 5-stage pipeline can distribute each instruction processing to 5 clock cycles, and 5 instructions are executed at the same time in each clock cycle. Under the same processing technology, the clock frequency of the ARM9 TDMI processor is 1.8 to 2.2 times that of the ARM7 TDMI.

2. Improvement of instruction cycle

Improvements in instruction cycles are very helpful in improving processor performance. The extent of performance improvement depends on the overlap of instructions when the code is executed, which is actually a problem of the program itself. For the most advanced language, generally speaking, the performance improvement is around 30%.

2.1 loads command and stores command

The most obvious improvement in instruction cycles is the loads and stores instructions. The execution time of these two instructions has been reduced by 30% from ARM7 to ARM9. The reduction in instruction cycles is due to the difference in the two basic microprocessor structures in the ARM7 and ARM9 processors.

(1) ARM9 has independent instruction and data memory interfaces, allowing the processor to fetch instructions and read and write data at the same time. This is called the modified Harvard architecture. ARM7 only has a data memory interface, which is used for both instruction fetching and data access.

(2) The 5-stage pipeline introduces independent memory and write-back pipelines, which are used to access the memory and write the results back to the registers respectively.

The above two points realize the completion of loads and stores instructions in one cycle.

2.2 Interlocks technology

When the data required by an instruction is not ready because the previous instruction has not been executed, a pipeline interlock occurs. When a pipeline interlock occurs, the hardware will stop the execution of the instruction until the data is ready. Although this technology will increase the code execution time, it provides great convenience for early designers. Compilers and assembly programmers can reduce the number of pipeline interlocks by redesigning the order of the code or other methods.

2.3 Branch Instructions

The branch instruction cycles of ARM9 and ARM7 are the same. Moreover, ARM9TDMI and ARM9ES do not perform prediction processing on branch instructions.

3 ARM9 structure and characteristics

Taking ARM9E-S as an example, the main structure and features of the ARM9 processor are introduced. The structure of ARM9E-S is shown in Figure 4. Its main features are as follows:

(1) 32-bit fixed-point RISC processor, improved ARM/Thumb code interleaving, enhanced multiplier design, and support for real-time debugging;

(2) On-chip instruction and data SRAM, and the memory capacity of instruction and data is adjustable;

(3) The capacity of on-chip instruction and data cache ranges from 4K bytes to 1M bytes;

(4) Setting up protection units is very suitable for segmenting and protecting memory in embedded applications;

(5) Using AMBA AHB bus interface to provide a unified address and data bus for peripherals;

(6) Support external coprocessors, and the instruction and data buses have simple handshake signaling support;

(7) Support standard basic logic unit scan test methodology and BIST (build-in-self-test);

(8) Support embedded trace macrocells and real-time trace of instructions and data.

4 Typical applications of ARM9

TI's OMAP730 is the latest wireless communication baseband signal processor. The processor is an integration of TI's GPRS Class 12 communication module and the ARM926 general-purpose processor (GPP) dedicated to application processing. Since the speed of the GPP can reach 200MHz, the OMAP730 has twice the application processing performance of the previous generation OMAP710 processor. Like all OMAP processors, the OMAP730 can support leading mobile operating systems, including Microsoft's smart phones and Pocket PC Phone Edition , Svmbian OS and Series 60, Palm OS and Linux.