Design of Direct Digital Frequency Synthesizer Based on Single Chip Microcomputer

1 Introduction

Frequency synthesis technology has gone through three generations: direct frequency synthesis technology, phase-locked loop frequency synthesis technology, and direct digital frequency synthesis technology. Direct digital frequency synthesis (DDFS or DDS) is the symbol of the third generation of frequency synthesis technology. Its main feature is that the computer participates in frequency synthesis, which can be realized by software, hardware, or a combination of the two. The biggest advantage of direct digital frequency synthesizer is that the frequency switching speed is extremely fast (up to several microseconds), and the frequency, phase and amplitude are all controllable. The output frequency stability can reach the stability level of the system clock, which is easy to integrate. More importantly, because the computer participates in frequency synthesis, the role of software can be fully utilized. Although the existing dedicated DDFS chip has many functions, the control method is fixed, so it may not be what we need. This article uses 80C51 single-chip microcomputer , D/A converter and some peripheral registers to design a direct digital frequency synthesizer. The circuit design is simple, the frequency control is flexible, it has good practicality, and the signal accuracy error is also within the allowable range.

2 Basic principles and overall block diagram of DDFS

DDFS basically consists of five parts: frequency code latch (FR), phase accumulator (PA), ROM (sine table), digital/analog converter (D/A), and low-pass filter (LPF), which work under the unified regulation of the clock.

First, divide the phase of a unit amplitude sine function into equally spaced points as small as possible within the range of 0 to 2π radians. If it is represented by an A-bit binary number and divided into 2A intervals, the minimum phase interval should be:

Calculate the unit sine function value of the corresponding phase point, and express it with a D-bit binary number, and write it into the ROM with A-bit address line and D-bit data line to form a so-called sine table. The process of synthesizing frequency is to control the change of phase increment (that is, the number of the minimum phase interval θmin of phase jump). Due to different phase increments, the sampling points in a sine cycle are different, and the sampling is carried out under the control of the system clock, that is, the sampling period is fixed. In this way, according to the accumulation of the phase increment and the corresponding point (representing the phase value), the period of the quantized sine wave formed by reading the corresponding function value from the ROM also changes with the change of the phase increment, thereby achieving the purpose of synthesizing the required frequency.

The phase accumulator accumulates once per clock according to the frequency code k in the frequency code latch. On the one hand, its output (N bit) returns to the other input end of the adder as the augend for the next accumulation, and on the other hand (A bit) is used as the address code of the ROM to address the ROM, read out the corresponding sine function value (binary code), and send it to the D/A converter after stabilization in the data buffer, and obtain a sine function value with an amplitude corresponding to the output phase point of the PA. When the next clock arrives, the accumulator increases another k value, and the ROM also reads the sine value corresponding to the A-bit address code output by the accumulator, and then sends it to the D/A converter. In this way, the output value of the phase accumulator is a step-type, and accordingly, the output of the D/A is a step wave with a sine as the envelope. The overflow of the phase accumulator corresponds to the end of one cycle of the step sine wave, and then the next cycle begins. After smoothing filtering by the low-pass filter, a sine wave with a frequency of f0 is obtained. Since the clock period Tc=(1/fc) is a constant and highly stable, the output frequency is also very stable.

The frequency resolution is:

The output frequency is:

Where N is the number of bits in the phase accumulator, and D is the frequency code. If N=A, the set k is the minimum number of phase intervals skipped by each clock PA. The increase of N means the improvement of frequency resolution, but the increase of A means the increase of ROM capacity, which makes the device more complicated, so generally N>A. The parameter settings in this design are: N=12, A=10, D=8.

3. Specific implementation of the main functional modules of the system

3.1 Frequency Code Latch (FR), Phase Accumulator (PA)

The frequency code latch is composed of two 8-bit D-type latches 74LS373. The second latch only uses D0 to D3 to form a 12-bit frequency code. The phase accumulator is composed of three 4-bit full adders 74LS283 to form a 12-bit adder. After passing through two registers 74LS273, the output of the adder is fed back to the input of the full adder as the addend (12 bits) on the one hand, and on the other hand (10 bits, discarding the lower 2 bits) as the address code to address the ROM, and the frequency code k output by the frequency code latch is used as the addend. Here, the register 74LS273 mainly plays the role of data buffering, and they all work on the rising edge of the clock.

3.2 ROM sine table

The ROM sine table is implemented using the program memory inside the 80C51 microcontroller. Since the address A output by the phase accumulator is 10 bits, and each sine function value is represented by an 8-bit binary number, the capacity of the sine table is 1 kB. The on-chip program memory capacity of the 80C51 is 4 kB, which is completely sufficient, so there is no need to expand the off-chip program memory. Use P3.1, P3.0 and P1.7~P1.0 of the 80C51 as the input port of the 10-bit address, use the table lookup program to read the corresponding function value according to the address, and then output it from the P0 port and send it to the D/A converter.

The so-called table lookup method is to find a table that satisfies certain accuracy requirements and represents the relationship between variables and function values ​​in advance, and then store this table in the program memory of the single-chip microcomputer. At this time, the independent variable is the unit address, and the corresponding function value is the content in the address unit. In microcomputer application systems, the tables generally used are linear tables. It is a most commonly used data structure, which is a collection of n data elements a1, a2, ..., an, and each element has a linear position relationship. Each time the table is looked up, first store the 10-bit address of P3.1, P3.0 and P1.7~P1.0 in the two units 20H and 21H (the high byte is at 20H), which will be used as the address offset when looking up the table (the actual address of the function value stored in the program memory = the table header address + offset).

3.3 Digital/Analog Converter (D/A)

The digital input of the digital/analog converter DAC0832 is 8 bits, and the working range of the reference voltage Vref is -10 to +10 V. Through it, an external high-precision voltage source is connected to the internal resistor network. There is an 8-bit input register and an 8-bit DAC register in the chip, forming a two-level buffer structure. In this way, the DAC can convert and output the previous data while transmitting the next data to the 8-bit input register to increase the speed of digital/analog conversion. The interface circuit of DAC0832 and 80C51 is shown in Figure 3. The P0 port of 80C51 is directly connected to the digital input DI7~DI0 of DAC0832, the WR of 80C51 is connected to the WR1 of DAC0832, and P2.7 is connected to the chip select terminal CS. The chip adopts a single buffer mode. At this time, the address of the chip is 7FFFH. [page]

3.4 System Clock Generation

The system clock can be generated by the timer/counter of 80C51. The clock frequency should be determined according to the highest output frequency, generally fc≥4f0max, and the cutoff frequency of the low-pass filter is the highest output frequency. In this design, the clock frequency requirement is 50 kHz, so a timer with a 20μs square wave output period is required. Select timer/counter T0, work in mode 0, and output to P2.0 pin. The 20μs square wave can be formed by alternating high and low levels at intervals of 10 μs, so P2.0 only needs to be inverted once every 10μs. Since the clock frequency of the 80C51 used in the experiment is 12 MHz, the initial count value is:

4 Software Design

4.1 ROM Lookup Program

5 Conclusion

A clear sine waveform can be seen by observing with an oscilloscope. By changing the frequency code k by a computer, waveforms of different frequencies can be obtained, and the output frequency increases with the increase of the frequency control word. However, when the output frequency exceeds 13 kHz, the output waveform is obviously distorted, which is mainly caused by the spurious generated by the D/A conversion, low-pass filtering and other parts. Since DDFS adopts a fully digital structure, spurious signals are inevitably introduced. There are three main sources: spurious signals caused by the phase truncation error of the phase accumulator, spurious signals caused by the amplitude quantization error (caused by the limited word length of the memory), and spurious signals caused by the non-ideal characteristics of the DAC.

The design of this article takes the generation of sine waves as an example. In fact, as long as different waveform data are stored in the waveform memory of DDFS, various waveform outputs can be achieved, such as triangle wave, sawtooth wave and rectangular wave, or even arbitrary waveform. In addition, as long as the corresponding control is added inside DDFS, such as frequency modulation control FM, phase modulation control PM and amplitude modulation control AM, the frequency modulation, phase modulation and amplitude modulation functions can be conveniently and flexibly realized to generate FSK, PSK, ASK and MSK signals. It has broad application prospects in the fields of communication, radar, electronic countermeasures, navigation, radio and television, remote control and telemetry, instrumentation, etc.