Application of Watchdog in Philips 8XC552 Series MCU System

1 Introduction

Philips' 8XC552 microcontroller is widely used in industrial control, DCS control and intelligent instruments due to its small size, powerful functions and low price. In the process of developing the intelligent power distribution monitor, although the author has taken corresponding anti-interference measures, due to the influence of electromagnetic fields, power grid spikes, harmonics, surges and lightning radiation in the industrial field environment, there may still be out-of-control phenomena such as program dead loops and runaway. For this reason, the author uses Watchdog technology to ensure the normal operation of the system. Usually, Watchdog technology can be divided into software Watchdog and hardware Watchdog in the microcontroller application system. Philips' 8XC552, Intel's 8098, Motorala's 68C05 and Microchip's 16C5X series microcontrollers already have software Watchdog functions. Therefore, as long as the hardware connection is correct, the corresponding statement can be called in the software design to start.

2 Hardware Composition Principle

2.1 System Working Principle

Figure 1 shows the connection circuit of 87C522 single-chip microcomputer for intelligent power distribution instrument. The 87C552 in this intelligent power distribution instrument is the main control chip. In addition to three 16-bit timers T0, T1 and T2, the chip also has a T3 timer dedicated to monitoring 8-bit timer, referred to as WDT (Watchdog Timer). Because the microcontroller is sometimes affected by environmental factors such as noise and radio frequency interference and enters an erroneous operating state. The function of the watchdog timer is to reset the microcontroller within a certain time limit, so as to recover it from the erroneous state and restart normal operation. When T3 is used as a watchdog timer and the timing is started by the software, if the system has reached the set predetermined time and still has not restarted the timer, an overflow signal will be generated and the timing will stop, indicating that the system is abnormal. The CPU can restart the timer, clear it, set the timing value, etc. When the system is running normally, the CPU will periodically restart the timer. Of course, its startup cycle should be less than the set value of the timer to ensure that the timer can never generate an overflow signal. When the system is not running normally, since the CPU cannot start the timer periodically, the timer will generate an overflow signal to force the CPU to resume normal operation of the system.

2.2 Watchdog's internal structure principle

The structural principle of the watchdog timer is shown in Figure 2. Its core is an 8-bit timer, and its predecessor is an 11-bit scaler. The latter's input signal is fosc/12, that is, the scaler counts the machine cycle incrementally. In this way, the value of timer T3 increases 1000 times every 2 machine cycles. If a 16MHz or 24MHz crystal oscillator is used, the increment interval of the watchdog timer will be 1.536ms and 1.024ms respectively; the corresponding maximum overflow period is 393.216ms and 262.144ms respectively.

When the watchdog timer overflows, the system will generate an internal reset pulse to reset the 8XC552. As shown in Figure 2, when T3 overflows, the transistor inside the RST pin is turned on instantaneously due to a negative pulse on the gate, thereby outputting a reset positive pulse on the RST pin with a width of 3 machine cycles. If the RST pin is connected to an external capacitor, such a narrow output pulse may be destroyed because the capacitor does not allow the RST pin voltage to change suddenly, but this will not affect the internal reset operation.

If the pin of 8XC552 is connected to a low level, the path of the input signal to the scaler will be unobstructed, so the monitoring timer will operate normally. However, if the pin is connected to a high level, the input signal will not pass because the AND gate is blocked, and the monitoring timer is in the off state. It should be noted that once T3 is turned on, it cannot be turned off by software; at the same time, if T3 is disabled by EW, it cannot be started by software.

If = 0, the PD bit of the PCON register cannot be written, its initial value is 0, and it cannot be set to 1, that is, it cannot enter the power-down mode. Therefore, the watchdog timer and power-down mode cannot be used at the same time.

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3 Common problems in debugging and their solutions

When debugging the system, there may be screen flashing, no display, or cluttered display. The solutions to these problems are introduced as follows:

(1) LCD screen flickers and the screen cannot be flipped

When I was programming with the simulator, the LCD could scroll and continuously display the collected three-phase power parameters. However, when the simulator was offline, the LCD could only display the first screen of data.

The pin was left floating, which caused the state of the pin to be unstable, and the internal reset signal was continuously generated to reset the microcontroller, resulting in the above phenomenon. Later, the pin was connected to a low level, and the above phenomenon still occurred. After the pin was connected to a high level (i.e., the Watchdog function was disabled), the LCD displayed normally. Therefore, the pin should be strictly prohibited from being left floating to avoid an unstable state. At the same time, before the Watchdog program is loaded, the pin should not be connected to a low level.

(2) LCD has no display

The capacitor at the RST end must be connected correctly, otherwise it will not be able to be added to the reset end when it is at a high level and the CPU will be unable to run the program, resulting in no LCD display.

(3) LCD display data is chaotic and data deadlocked. If the pin is connected to a low level, the LCD display data may be chaotic and data deadlocked. The reason is that the Watchdog program is not loaded in the source program. Therefore, the Watchdog program should be added to the source program to eliminate problems such as data deadlock or chaotic display.

4 Software Design

4.1 Software Design

When writing software to run the watchdog timer, the programmer should first determine the time the system can support in an error state, which is the basis for setting the overflow cycle. For example, if it can maintain 16ms, the initial value of T3 is set to 10. In this way, in the case of a 16MHz crystal oscillator, the overflow cycle is 15.36ms. At this time, the programmer can divide his software to determine where to insert the instruction to rewrite the T3 value so that the interval between two adjacent rewrite operations does not exceed the overflow cycle of the watchdog timer to ensure that T3 does not overflow during normal operation. Therefore, the programmer should understand the execution time of all software modules, and also consider the impact of factors such as conditional jumps, subroutines, and internal and external interrupts. For those program sections whose execution time is difficult to estimate, the worst case estimate should be used. To prevent miswriting, the rewriting of the watchdog timer value can be carried out in two steps. First, set PCON.4 (watchdog timer load enable bit WLE) to 1 to allow writing to T3; the second step is to write a new value to T3. As shown in Figure 2, the write signal to T3 is also added to the clear terminal of WLE, so whenever a new value is written to T3, the WLE bit is automatically reset. Therefore, when the value is 00H, the overflow interval is the largest; and the FFH value corresponds to the minimum overflow period. If a 12MHz crystal oscillator is used, these two values ​​are 524ms and 2ms respectively. The calculation formulas for the maximum and minimum overflow periods are:

Since the watchdog timer runs normally in idle mode, this mode is contradictory to the power-down mode, because the former requires a clock, while the latter freezes the clock. Therefore, when = 0 and T3 is turned on, the 8XC552 will not be able to enter the power-down mode. At this time, the operation of writing l to PCON.1 is invalid, so it will remain 0. In the early stage of software development and debugging, the pin can be connected to a high level to turn off the watchdog timer, and then connected to a low level to complete the debugging process in the later stage.

4.2 Setting the timing interval and access time

Data acquisition and processing are the key parts of the program and are also the key to determining the accuracy of the instrument. This instrument uses voltage, current, frequency, and phase as the main acquisition parameters, and these parameters are continuously changing, so the sampling time should not be set too long, otherwise it will affect the accuracy of the instrument. The author sets the sampling time of current and voltage to 5ms, and the acquisition time of frequency and phase to 20ms. In this way, the timing interval of Watchdog is better, as shown in Figure 3. In Figure 3, Watchdog completes the monitoring of the acquisition frequency data within the WDT1 time, and is responsible for monitoring the voltage, current, and phase data acquisition in WDT2, WDT3, and WDT4 respectively. When designing a program, 1.1Ts is generally taken.

4.3 Software Program

This intelligent monitoring instrument is programmed in C language and uses a 12MHz crystal oscillator. Its overflow time should be set to 6ms, 20ms, 524ms, etc. Therefore, the Watchdog programs that should be added to the source program in due time are as follows:

5 Conclusion

After adding Watchdog to the source program of the intelligent power distribution instrument, the operation of the entire system will be more stable and reliable, thus effectively overcoming various interferences from industrial power consumption sites.