Design of a large-capacity recording system for digital video compression

introduction

With the rapid development of computer technology, multimedia and data communication technology, digital video is increasingly used in applications such as video surveillance, video conferencing and mobile TV. The huge amount of digital video data is not conducive to transmission and storage, which greatly limits its application. To solve the problem of video data storage and transmission, the only way is to compress the video data. Common video compression methods include MPEG series and H.26x series. Considering the maturity, cost and main uses of compression technology, MPEG-1 is used as the compression standard to design an embedded digital video recording system based on ARM processor. The system is suitable for a variety of applications such as video surveillance and video conferencing. It can also be installed on aircraft to record various information during the flight and training of the aircraft in real time.

At present, there are a large number of MPEG-1 video compression cards based on PCI bus and network video servers based on PC architecture on the market. Compared with them, the video recording system we designed has the advantages of low cost, small size and low power consumption.

1 System Working Principle

The design of the video compression recording system focuses on the embeddedness of the controller and the overall portability. This system mainly consists of three parts, namely the compression part, the control part and the storage part. The structure of the video recording system is shown in Figure 1. The compression part is composed of the MPEG1 audio and video compression circuit, and its main function is to realize the decoding, digitization and compression encoding of the input audio and video signals, and generate MPEG1 program stream and transmission stream; the control part is composed of the ARM minimum system, which is used to realize the control of the entire system, data flow management and IDE interface control; the storage part is composed of a large-capacity hard disk or CF memory card to realize real-time and long-term recording of compressed data.

When the system starts, the ARM processor initializes the entire compression system. First, the internal registers of SZ1510 are configured through the HOST interface, and the video decoder SAA7113H is initialized using the serial interface of SZ1510 to simulate the I2C bus. After the compression format and data rate of MPEG-1 are set, the system starts to work normally. The audio and video signals are converted by A/D through the AK4550 audio processing chip and the SAA7113 video processing chip, and the 8-bit PCM format digital audio signal and 4∶2∶0 YCbCr digital video signal are output, which are then sent to the SZ1510 audio and video compression acquisition chip for processing, and the digital audio and video data are converted into mixed video files that conform to the MPEG-1 format. Finally, the MPEG1 data stream is written to the hard disk or CF card through the IDE interface under the control of the ARM processor. When working, ARM will also continuously monitor the relevant signals and add corresponding signs to the image until the shutdown signal is received, and the system automatically ends the compression work.

2 Hardware Circuit Design

Since the MPEG-1 compression algorithm requires a lot of computation, it is difficult to complete it in real time with software. Therefore, in this system, the efficient compression of video signals is mainly achieved by special chips. At present, the commonly used MPEG-1 compression chips include VW2010, W99200F, WIS 7007SB, etc. This design uses Zapex's SZ1510 MPEG-1 A/V encoding chip, which completes the synchronous encoding of audio and video by itself, and the 16-bit HOST interface is easy to connect with a variety of microprocessors. In addition, the chip can also directly control the video decoding chip SAA7113H, the audio decoding chip AK4550VT and SDRAM (KM416S1020CT-G10). The CPU uses Philips' ARM7TDMIS core microcontroller LPC2214, which controls the data reading and storage of the IDE interface hard disk or CF card through its I/O port.

Figure 1 Block diagram of digital video recording system

2.1 MPEG-1 Compression Circuit Design

SZ1510 is an MPEG-1 and motion JPEG image encoder. Its built-in video compression core is optimized for efficient and real-time MPEG1 digital image compression, with multiple functions, low power consumption, and wide temperature range. It also integrates TI's TMS320C54X high-performance DSP core, which can encode audio and video synchronously according to the MPEG-1 standard.

(1) Clock synchronization circuit setting
SZ1510 is a complex video compression system that needs to complete audio and video synchronization, MPEG-1 video compression, and system internal data stream compounding and scheduling; the clock relationship is relatively complex, which is a difficulty in system design. The clock configuration can be divided into the main clock, audio and video clock, video compression core clock, DSP core clock, and extended I2S interface clock. Their functions and relationships are as follows:
◆ Main clock. The main clock of SZ1510 is a stable 27 MHz (CLK). This clock is multiplied to 81 MHz by PLL1 inside the chip to drive the video compression core and SDRAM of SZ1510. PLL2 is connected to the DSP core and configured by software to work at 94.5 MHz for audio compression and system data stream compounding.
◆ Audio and video clock. The video clock comes from the video decoder, with a typical value of 27 MHz. The audio clock is generated by dividing the video clock.
◆ I2S interface clock. In this system, the slave mode of I2S interface is used in the audio and video synchronization design, and the serial clock and frame synchronization signals are generated by SZ1510.

(2) Host (HOST) port settings
SZ1510 as a slave device, controlled by the host, its HOST interface is the control and data exchange interface of SZ1510. SZ1510 can choose multiplexed or non-multiplexed Intel and Motorola bus types; non-multiplexed bus can be divided into 8-bit and 16-bit. The specific host port is configured by the HCONFIG[1∶0] pin and the SysConfig[3] register. In this system design, HCONFIG0 is pulled low and HCONFIG1 is pulled high through the jumper to make it work in the Intel 8051 type non-multiplexed 16-bit data bus mode. [page]

2.2 LPC2214 microprocessor circuit design

LPC2214 is a 32-bit ARM7TDMI-S-based CPU that supports real-time simulation and tracing. It has 16 KB on-chip SRAM, 256 KB embedded high-speed Flash memory, 128-bit memory interface and unique acceleration structure, which enables 32-bit code to run at a maximum clock rate of 60 MHz. A variety of serial interfaces are integrated inside the chip. The interface and control relationship between LPC2214 and SZ1510 is shown in Figure 2. In the design, it is important to keep the SZ1510 read and write timing synchronized with the internal clock. The exchange of control words and data is achieved by selecting SZ1510 through CS3.

Figure 2 Interface relationship between LPC2214 and SZ1510

2.3 IDE interface design

Since the LPC2214 chip does not have an IDE interface, a general I/O port is used in this system to simulate the read and write timing of the ATA device to achieve reliable read and write operations on the IDE hard disk. Figure 3 is a diagram of the connection between LPC2214 and the IDE hard disk. Among them, P2.16~P2.31 are used as data lines, P1.16~P1.20 are used as address and selection signals, P0.17 and P0.20 are reset and status request signals for the device, and P0.21 and P0.19 are used to implement read and write control.

Figure 3 LPC2214 and IDE hard disk connection diagram

3 System Software Design

The system software consists of a main program and several subprograms, and the workflow is shown in Figure 4. The main submodules are: SZ1510 settings and control, IDE interface driver, and file system management.

Figure 4 System workflow

3.1 SZ1510 settings and control

SZ1510 has 128 registers, each with an index number. When SZ1510 works in non-multiplexed bus mode, external access to registers is done through IOAR and IODR. When accessing, first write the index number of the register into IOAR, and then write the data to be written into IODR.

The setting and control process of SZ1510 is as follows:
① Write 0x40 to the interrupt enable register to enable the Ready interrupt;
② Wait for the Ready interrupt of SZ1510;
③ After the Ready interrupt, write 0x0A to the 0x1E register of SZ1510 to set its internal DSP clock to 94.5 MHz;
④ Write 0x55 to the 0x013 register to soft reset SZ1510;
⑤ Write 0x40 to the interrupt enable register 0x0C to enable the Ready interrupt;
⑥ Wait for the RDY interrupt;
⑦ Initialize SAA7113 after the Ready interrupt;
⑧ Soft reset SZ1510, that is, write 0x55 to the 0x0B register and write 0x40 to the 0x0C register at the same time;
⑨ Wait for the Ready interrupt, and then load the binary code to the internal DSP of SZ1510;
⑩ Load the binary code of the internal video compression core of SZ1510. The specific loading steps are as follows:

◆ Write 0x04 to register 0x08 and send a start command;
◆ Wait for the Ready interrupt and clear the Ready interrupt;
◆ Write 256 bytes to the Data in register 0x01;
◆ Wait for the End of Data interrupt and then clear the interrupt;
◆ Check whether the code in the program space has been loaded. If not, continue loading.

3.2 IDE interface driver

This system uses the general programmable I/O port of LPC2214 to simulate the read and write timing of ATA devices to realize the reading and writing of hard disks. Here are the steps for simulating writing ATA device registers (the steps for reading ATA device registers are similar):

① Turn off system interrupts to prevent interrupts during register write operations;
② Set the GPIO emulating ATA interface data pin to output status and prepare to output data to the device data line;
③ Set the corresponding address of the ATA device register;
④ Set the GPIO emulating ATA interface data pin level to the value to be written to the device;
⑤ Make the write ATA device register signal low level;
⑥ Make the write ATA device register signal high level;
⑦ Cancel the selection of the ATA device register address;
⑧ Set the GPIO emulating ATA interface data bus pin to input status and release the bus;
⑨ Turn on system interrupts.

3.3 File System Management

This design uses a small file system ZLG/FS [1] for embedded systems, which is mainly used to store data in a standard file format and manage the entire file system. At the same time, in order to facilitate the retrieval and query of audio and video, and to prevent the loss of a large amount of unsaved data caused by illegal power outages, the system is set to store compressed data in a new file named after the system time every certain interval (30 minutes).