Design of VGA Display System Based on Embedded CPU S3C2440

At present, many SOC manufacturers' microprocessor chips have integrated LCD controllers, such as Samsung's S3C2410.S3C2440, Intel's Xscale series, etc. Most embedded systems also use popular LCD display technology. However, in places where large-screen display is required and resolution is not required, such as workshops and factories, the cost of using large-screen LCD is too high. On the other hand, VGA display technology is still widely used because of its mature technology and low cost. Until today, it is still the most mature standard interface for all display terminals. If the embedded processor directly supports VGA display, it can make great use of existing resources and save system costs.

1 Analysis of VGA display technology based on S3C2440

By analyzing the timing logic of VGA display technology and the timing logic of the S3C2440 internal integrated LCD controller driving TFT LCD, we can find out their common points and analyze the feasibility of applying VGA display interface on S3C2440.

1.1 VGA Display Principle

VGA (Video Graphics Arrnay) is a display interface proposed by IBM and is still widely used in PCs. This interface has the advantages of high resolution, fast display speed, and rich colors, and has been widely used in the field of color displays. The VGA interface is physically a DB15 socket, and the VGA adapter uses a female DB15 standard interface. Its pin definition is shown in Table 1.

Table 1 VGA adapter pin definition

The VGA interface uses analog RGB channels, scanning point by point and line by line. Its timing is shown in Figure 1. The VGA interface signal is an analog signal, and there are five key signals, namely Horizontal Sync horizontal synchronization signal (also called line synchronization signal), Vertical Sync signal (also called field synchronization signal), red analog signal, green analog signal and blue analog signal. The electron gun scans from left to right and from top to bottom. At the end of each line, it is synchronized with the line synchronization signal. After scanning all the lines, the field synchronization signal is used for field synchronization. Because the electron gun deflection takes time, the electron gun must be blanked during the rotation after scanning. Line blanking is performed during the rotation process after the end of each line, and field blanking is performed during the rotation process after the end of each field. No electron beam is sent during the blanking process.

Figure 1 VGA scanning timing

1.2 TFT LCD display scanning timing analysis

The S3C2440 chip based on the ARM920T core integrates an LCD controller on the periphery. The LCD controller is used to transmit image data to the LCD and provide necessary control signals, such as VFRAME, VLINE, VCLK, VM, etc. In addition, the LCD controller also includes a set of control registers: LCDCON1 register, LCDCON2 register, LCDCON3 register, LCDCON4 register, LCDCON5 register. The settings of these registers are closely related to the display information, control timing and data transmission format. In the design, these registers need to be correctly set according to the specific information of the display device in order for the S3C2440 to control and drive different display screens normally.

The scanning sequence of a typical TFT liquid crystal display is shown in Figure 2.

Figure 2 Typical TFT LCD scanning timing

These mainly include:

1) Frame (vertical) synchronization (VSYNC): A high level (or low level) is used to indicate the start of scanning a frame.

2) Line (horizontal) synchronization (HSYNC): A high level (or low level) is used to indicate the start of scanning a line.

3) Clock (VCLK): Writes data to the LCD screen through the rising edge (or falling edge).

4) Data valid control (VDEN): Indicates whether TFT output is turned on.

5) Data signal (VD): represents the color of each dot, usually in 16-bit, 18-bit, 24-bit and other modes.

By comparing the timing of the VGA interface and the scanning timing of the TFT LCD display, it can be seen that they are very similar. This provides an inherent possibility for driving the VGA display with an LCD controller. Moreover, once this conversion solution is implemented, since the electrical conversion of the two interfaces is implemented by hardware, no driver program needs to be written. It is the most convenient solution for expanding the VGA interface on the embedded system platform. Comparing the characteristics of the two interfaces, to achieve the conversion from TFT timing to VGA timing, the following problems need to be solved: [page]

1) The level problem of TFT LCD scanning synchronization signal and VGA synchronization signal.

2) The output of the TFT LCD controller is an RGB digital interface, while the red, green and blue channels of VGA are analog quantities, and both need to be converted through D/A. When using D/A, issues such as conversion accuracy, conversion speed, and the number of conversion channels must be considered. Among them, to meet the requirements of true color (24 bits), 8-bit conversion accuracy is sufficient. Based on the frame rate requirements of VGA, the conversion frequency of each point must be greater than 27 MHz, and at least 3 channels must be converted simultaneously to meet the output of the 3 channels of red, green and blue (RGB).

The D/A for this type of conversion is usually called a video D/A. This design uses ATI's video D/A chip ADV7120.

1.3 ADV7120 Introduction

ADV7120 is a high-speed video digital-to-analog conversion chip produced by ADI in the United States. Its pixel scanning clock frequency has three levels: 30, 50, and 80 MHz. ADV7120 integrates three independent 8-bit high-speed D/A converters on a single chip, which can process red, green, and blue video data separately. It is particularly suitable for display terminals with high-resolution analog interfaces and application systems requiring high-speed D/A conversion.

The input and control signals of ADV7120 are very simple: 3 groups of 8-bit digital video data input terminals, corresponding to RGB video data respectively, and the data input terminals use standard TTL level interface; 4 video control signal lines include composite synchronization signal SYNC, blanking signal BLANK, white level reference signal REFWHITE and image clock signal CLOCK; an external 1.23 V digital-to-analog conversion reference voltage source and an output full-scale adjustment. There are only 4 output signal lines: analog RGB signals use high-resistance current source output mode, which can directly drive 75 Ω coaxial transmission lines; the synchronous reference current output signal Isync is used to encode video synchronization information in the green video analog signal.

2 VGA interface circuit design

As mentioned above, the timing of the VGA interface is consistent with the timing of the LCD scanning interface. The structural block diagram of the conversion module from the TFT liquid crystal timing to the VGA interface composed of ADV7120 is shown in Figure 3.

Figure 3 VGA interface circuit block diagram

According to the data sheet of ADV7120, ADV7120 has very high requirements for reference level and cannot be replaced by a resistor divider circuit. In this design, a 1.235 V voltage reference chip AD589 is used to generate the reference voltage.

3 VGA display mode selection and corresponding control register settings in S3C2440 LCD controller

Initially, VGA display included several modes. Initially, the resolution of VGA was defined as 640x480. Then, higher resolution standards such as SVGA and XVGA were proposed on this basis. The interfaces are compatible with the VGA standard, so all such interfaces are usually called VGA interfaces. Different display modes correspond to different time parameters in the VGA timing. After selecting a display mode, the LCD controller must be configured so that the timing parameters it generates meet the requirements of the VGA mode. Only in this way can the VGA interface be successfully driven. Otherwise, the VGA display end will flicker, be blurred, or even not display.

Here, select the VGA display mode with a resolution of 640x480, a refresh rate of 60 Hz, and 16-bit color, and complete the configuration of the LCD controller's related registers in this mode. Make the timing logic output by the LCD controller meet the requirements of VGA display in this mode. In this mode, the timing of the VGA interface synchronization signal is shown in Figure 4.

Figure 4 VGA interface synchronization signal timing

Next, the control registers in the main LCD controller are configured according to the VGA interface synchronization signal timing of Figure 4:

1) LCDCON1 register

CLKVAL: Parameter that determines the VCLK frequency. The formula is VCLK-HCLK/[(CLKVAL+1)x2]. In this design, the HCLK of S3C2440 is 100 MHz, and the display requires VCLK=20MHz, so CLKVAL=1 is required.

BPPMODE: Determines the BPP (bits per pixel). Selecting BPPMODE=0xC selects TFT 16-bit mode. [page]

2) LCDCON2 Register

VBPD: Determines the delay between the frame synchronization signal and the frame data transmission. It is the ratio of the delay time before the frame data transmission to the width of the line synchronization clock interval. Referring to the time data in Figure 4, VBPD=t3/t6=1.02 ms/31.77 μs=32.

LINEVAL: Determines the vertical size of the display. Formula: LINEVAL=YSIZE-1=479.

VFPD: Determines the delay from the completion of frame data transmission to the arrival of the next frame synchronization signal. It is the ratio of the delay time after frame data transmission to the width of the line synchronization clock interval. From the time data in Figure 4, VFPD=t5/t6=0.35 ms/31.77μs=11.

VSPW: Determines the frame synchronization clock pulse width, which is the ratio of the frame synchronization signal clock width to the line synchronization clock interval width. As shown in Figure 4, VSPW=t2/t6=0.06 ms/31.77 μs=2.

3) LCDCON3 Register

HBPD: Determines the delay between the horizontal synchronization signal and the horizontal data transmission, and describes the number of VCLK pulses in the delay time before the horizontal data transmission. As shown in Figure 4, VBPD = t7xVCLK = 1.89 μsx25 MHz = 47.

HOZAL: Determines the horizontal size of the display. Here HOZAL=XSIZE-1=639.

HFPD: Determines the delay time from the completion of row data transmission to the arrival of the next row synchronization signal, and describes the number of VCLK pulses during the delay time after row data transmission. As shown in Figure 4, HFPD=t9xVC LK=0.94 μsx25 MHz=24.

4) LCDCON4 register

HSPW: Determines the horizontal synchronization clock pulse width. Describes the number of VCLK pulses within the horizontal synchronization pulse width time. As shown in Figure 4, HSPW=3.77 μsx25 MHz=94.

5) LCDCON5 Register

BPP24BL: Determine the data storage format. Here, set BPP24BL=0x0, which means that the little-endian mode is selected for storage.

FRM565: Determine the 16-bit data output format. Set FRM565 = 0x1 to select the 5:6:5 output format.

By designing the VGA interface circuit in the above manner and setting the LCD controller registers accordingly, a seamless connection between LCD digital output and D/A conversion is achieved, and the image information originally output on the LCD can be output to the VGA display without any additional driver.

4 Tests and Conclusions

This design analyzes the similarities between the VGA interface timing and the S3C2440 TFT LCD interface timing, and demonstrates the feasibility of using the S3C2440 built-in LCD controller to drive the VGA display. Timing matching is the most critical part of the success of this design. Under the premise of meeting the interface timing requirements, a high-speed three-way 8-bit video D/A chip is used to convert the digital RGB signal of the LCD interface into the analog signal required by the VGA interface. Experiments have shown that the image information is displayed well on the display screen through the VGA conversion circuit without obvious jitter, meeting ordinary display requirements. Since the host uses an ARM embedded microprocessor, the cost of the entire system is greatly reduced compared to the traditional X86 host. This cheap and simple display solution can be widely used in various occasions that do not require high display effects but require large-size screens.