Design and application of wireless transmission circuit based on TRF4900

1 Wireless digital transmission circuit

The wireless digital transmission circuit uses the wireless transmission chip TRF4900. TRF4900 is a monolithic, low-cost, fully functional multi-channel FSK transmitter produced by TI. The chip can meet the linear (FM) or digital (FSK) transmission applications in the European 868 MHz band and the North American 915 MHz ISM band. The monolithic transmitter chip has an operating voltage of 2.2 to 3.6 V, a typical transmission power of 7 dBm, and low power consumption. The 24-bit direct digital synthesizer has an 11-bit DAC, and the synthesizer has a channel space of about 230 Hz, allowing narrowband and broadband applications. Two fully programmable operating modes, mode 0 and mode 1, allow very fast conversion between two pre-programmed settings (such as transmission frequency 0 or transmission frequency 1). The chip integrates a voltage-controlled oscillator (VCO), a phase-locked loop (PLL) and a reference oscillator, and only requires very few external components to form a complete transmission circuit. TRF4900 is connected to the TI MSP430 microcontroller via a serial interface. Each functional block of the transmitter can be programmed through the serial interface to set its function. The TRF4900 application circuit is shown in Figure 1. 2 Connection circuit with microcontroller

The TRF4900 connects to TI's MSP430 microcontroller via a serial interface, as shown in Figure 2.

Pin 23 (LOCKDET) of the TRF4900 is the PLL phase lock detection output, valid as high. When LOCKDET = 1, the PLL is locked. Pin 11 (MODE), the mode selection input, the device's functions in mode 0 and mode 1 can be programmed through the A, B, C, D words of the serial control interface. Pin 12 (), sleep control, is valid at low level. When = 0, the contents of the control register are still valid and can be programmed through the serial control interface. Pin 14 (TX-DATA), digital modulation input, is FSK/FM modulation of the carrier, valid at high level.

The serial control interface is a 3-wire unidirectional serial bus (CLOCK serial interface clock signal, DATA serial interface data signal, STROBE serial interface selection signal) used to program the TRF4900. The registers inside the interface contain all user programmable variables, including DDS frequency settings, as well as all control registers. The timing of the serial interface is shown in Figure 3.

At each rising edge of the CLOCK signal, the logic value on the DATA pin is written into the 24-bit shift register. Set the STROBE terminal to a high level and the programmed information is loaded into the selected latch. When the STROBE signal is high, the DATA and CLOCK lines must be low. Therefore, the STROBE and CLOCK signals are asynchronous. The serial interface can be programmed to work in an active state or a sleep state (standby mode). [page] 3 TRF4900 settings

The direct digital synthesizer DDS of TRF4900 is based on the digital method of generating sine wave signals. DDS consists of an accumulator, a sine wave lookup table, a digital/analog converter, and a low-pass filter. The clock of all digital function blocks is provided by the reference oscillator. DDS uses an N-bit adder to count from 0 to 2N and generate a digital step wave according to the data conversion specification in the frequency register to construct an analog sine wave. Each digit of the output register of the N-bit counter is used to select the corresponding sine wave value output in the sine wave lookup table. After the digital/analog conversion, the low-pass filter is used to suppress unwanted parasitic responses. The analog output signal can be used as a reference input signal for the PLL. The PLL circuit multiplies the reference frequency according to a predetermined coefficient.

The frequency fref of the reference oscillator is the sampling frequency of the DDS, and also determines the maximum DDS output frequency. Together with the number of bits of the accumulator, the frequency resolution of the DDS can be calculated. The minimum frequency step of the TRF4900 can be calculated by the following formula:

Δf=N×(fref/2 24)

The 24-bit accumulator can be programmed through two 22-bit frequency setting registers (the A word determines the frequency of mode 0 and the B word determines the frequency of mode 1), and the two MSB bits of the registers are set to 0. Therefore, the maximum bit weight of the DDS system is reduced to 1/8, as shown in Figure 4.

This bit weight corresponds to the VCO output frequency (fref/8) × N. Depending on the logic level at the MODE terminal, the internal selection logic loads the DDS-0 or DDS-1 frequency into the frequency register. The VCO output frequency fout is determined by the DDS-x frequency setting (DSS-0 in the A word, DDS-1 in the B word). The VCO output frequency fout is calculated as follows:

fout=DDS_x×N×(fref/2 24)=N×[(fref×DDS_x)/2 24]

If FSK modulation is selected (MM = 0, C word, 16 bits), the 8-bit FSK frequency deviation register can be used to program the frequency deviation of 2-FSK modulation. The 8 bits of the frequency deviation register are in the 24-bit DDS frequency register, and the LSB is set to 0. The total FSK frequency deviation is calculated by the following formula:

Δf2-FSK=N×[(DEV×fref)/2 22]

Therefore, the 2-FSK frequency is set by the level on TX-DATA, calculated as follows:

fout1:TX_DATA=low=N×[(fref×DDS_x)/2 24]

fout2:TX_DATA=High=N×[fref×(DDS_x+4×DEV)]/2 24

This frequency modulated output signal is used as the reference input signal of the PLL circuit. 2-FSK modulation channel width (frequency deviation) and channel spacing are software programmable. The minimum channel width and minimum channel spacing depend on the RF system frequency design, center frequency fcenter = (fout1 + fout2)/2. When FSK is transmitted, the center frequency fcenter is considered to be the effective carrier frequency.

The phase-locked loop consists of a phase detector (PD), a frequency discriminator (PD), a charge pump, a VCO, an external loop filter, and a programmable pre-divider (N divider) in the feedback loop. When an external VCO is used, the x-VCO bit will be set to 0. The divider is programmable, and the division factor N can be set to 256 or 512 by the C word.

The power amplifier (PA) can be programmed by the two bits P0 and P1 in the D word to provide variable output power levels.


The control word of the TRF4900 is 24 bits. The first introduced bit is the most significant bit (MSB) to complete the programming of the TRF4900; four 24-bit words must be set, that is, the A, B, C, and D words must be set. Figure 5 shows the four defined control words. Tables 1, 2, and 3 describe the function of each parameter, and Table 4 shows the transmit frequency in FSK mode. [page]

Table 1 Mode 0 Control Register Description

Table 2 Mode 1 Control Register Description

Table 3 Auxiliary control register description

Table 4 Transmit frequency in FSK mode (MM bit set to 0)

Conclusion

The wireless digital transmission circuit composed of TRF4900 and MSP430 can be easily embedded in various measurement and control systems; it is used in instrument data acquisition systems, wireless meter reading systems, wireless data communication systems, computer telemetry and remote control systems, etc.