EMC Design for Automotive Electronics

Automotive electronics are in a noisy environment , so automotive electronics must have excellent electromagnetic compatibility (EMC) performance. The most important part of automotive electronics EMC design is the design of the microprocessor. The author will combine actual design experience to analyze the noise generation mechanism and propose methods to eliminate noise.

Automotive electronics often work in harsh environments: ambient temperatures range from -40oC to 125oC; vibration and shock occur frequently; there are many noise sources, such as wiper motors, fuel pumps, spark ignition coils, air conditioning starters, intermittent disconnection of alternator cable connections, and certain wireless electronic devices, such as mobile phones and pagers.

Automotive designs generally have a highly integrated microcontroller that is used to perform a large number of calculations and implement control related to vehicle operation, including engine management and brake control. Automotive electronic design not only needs to protect the MCU in this noisy environment, but also must standardize the MCU module design to ensure that the noise emitted by the MCU module meets the relevant specifications.

Conceptually, electromagnetic compatibility (EMC) includes two parts: the system's own sensitivity to noise and noise emission. Noise can be transmitted through electromagnetic fields to generate radiated interference, or it can be conducted through parasitic effects on or off the chip.

EMC is becoming increasingly important in most automotive control system designs. If a designed system does not interfere with other systems, is not affected by other system emissions, and does not interfere with the system itself, then the designed system is electromagnetically compatible.

Any electronic device and system sold in the United States must comply with the EMC standards set by the Federal Communications Commission (FCC), and major American automakers also have their own set of test specifications to constrain their suppliers. Other automotive companies usually have their own requirements, such as:

SAE J1113 (Electromagnetic Susceptibility Test Procedure for Automotive Devices) provides the recommended test levels and test procedures for automotive devices.

SAE J 1338 provides information on how to test the electromagnetic susceptibility of the entire vehicle.

SAE J1752/3 and Parts 2 and 4 of IEC 61967 are two standards dedicated to IC emissions testing.

Europe also has its own standards. The EU EMC directive 89/336/EEC came into effect in 1996, and since then the European automotive industry has introduced a new EMC directive standard (95/54/EEC).

Checking the sensitivity of the vehicle to electromagnetic radiation should ensure that the reference level is limited to 24V/m RMS in the 90% bandwidth range of 20 to 1000MHz throughout the vehicle, and the RMS value in the entire bandwidth is within 20V/m. During the test, the driver's direct control of the steering wheel, brakes and engine speed should be tested, and no abnormalities that may cause confusion to anyone else on the road or abnormalities in the driver's direct control of the vehicle are allowed.

As the chip geometry continues to decrease and the clock speed continues to increase, the device will emit clock harmonics exceeding 500MHz, so EMC design is very important. For example, Motorola's latest microcontroller MPC5500 series based on the e500 architecture uses 0.1 micron process technology and has a clock frequency of 200MHz.

In addition, the requirements of product cost force manufacturers to design circuit boards without using ground planes and to reduce the number of components as much as possible. Automotive design engineers will face very strict design constraint challenges. The designed electronic system must be highly reliable. Even a simple fault in one car in a million is not allowed. The fact that all cars are recalled without considering EMC design proves that this practice is not only a huge loss, but also affects the reputation of the automobile manufacturer.

In electromagnetic compatibility design, the concept of "victim" usually refers to those components that are affected by the lack of EMC considerations in the design. The victim components may be inside the MCU-based PCB or module, or they may be external systems. Common victim components are broadband receivers in keyless-entry modules or garage door opener receivers. Due to strong enough noise from the MCU, the receivers in these modules will mistakenly believe that they have received a remote control signal.

Car radios are also often victims: the MCU can generate a large number of FM band harmonics, seriously degrading the sound quality. Other modules distributed in the car may be similarly affected, and the transmission noise generated by the MCU-based module will be propagated through the cables. If the MCU generates enough noise to interfere with text and voice, then cordless phones and pagers are also susceptible to interference.

EMC Design

Many EMC design techniques can be applied to circuit boards and SoC design. The most common parts are transmission line effects, as well as parasitic resistance, capacitance, and inductance effects on wiring and power distribution networks. Of course, there are many technologies related to the chip itself in SoC design, involving substrate materials, device geometry, and packaging.

First, understand the transmission line effect. If there is an impedance mismatch between the transmitter and the receiver, the signal will be reflected and cause voltage ringing, thereby reducing the noise margin, increasing signal crosstalk, and generating signal emission interference through capacitive coupling. The transmission line size on the IC is usually very small, so it will not emit noise or be affected by radiated noise, while the transmission line size on the circuit board is usually large, which is prone to this problem. The most common solution is to use a series terminator.

In SoC design, noise is mainly conducted through parasitic resistance and capacitance rather than radiated in the form of electromagnetic fields. CMOS chips enhance their anti-latching capabilities by using an epitaxial process to achieve an extremely low resistance substrate, while the bottom side of the substrate provides an effective conduction path for substrate noise, making it difficult to electrically separate the noise source from the sensitive node.

Many parallel p+ substrate contacts provide a low impedance path for resistively coupled noise. Parasitic capacitance is formed between the sidewalls and bottom of the n-well and the p-substrate of the p-channel transistor, thus generating capacitively coupled noise, and a pn junction is formed between the substrate and source region of the n-channel transistor (see Figure 1).

The capacitance of a single pn junction is very small. The sum of the parallel capacitances in a VLSI SoC design is usually several nanofarads. This capacitance can be short-circuited by directly connecting the source region to the substrate before connecting to the power network. This technique also eliminates the body effect caused by the instantaneous negative current entering the substrate. The body effect increases the depletion region and causes the Vt of the transistor to become higher. The same technique can also be applied to n-well p-channel transistors to reduce capacitive coupling noise.

However, digital or analog circuits containing stacked transistors usually require isolated source regions. In this case, increasing the capacitance from Vss to substrate or Vdd to substrate can reduce noise transients. For analog circuit design, body effect reduces circuit performance by changing bias current and signal bandwidth, so other solutions such as well isolation are needed. For digital circuits, a single well is ideal to reduce chip area. Body effect can be compensated through careful design. [page]

Another source of substrate noise is impact-ionization current, which is process technology-dependent and occurs when the NMOS transistor reaches the pinch-off voltage. Impact ionization generates hole current (positive transient current) in the substrate.

Typically, the frequency range of the substrate noise may be as high as 1GHz, so the skin effect must be considered. The skin effect refers to the increase in inductance with increasing depth on the conductor, reaching a maximum value at the center of the conductor. The skin effect causes attenuation of the on-chip signal and distortion of the signal in the p+ substrate layer of the chip. To minimize the skin effect, the substrate thickness is required to be less than 150 microns, which is much smaller than the minimum mechanical thickness allowed for some substrates, but thinner substrates are more fragile.

Noise Source

There are four main sources of noise inside the microcontroller: currents in the power and ground lines generated by synchronous switching of internal buses and nodes; changes in output pin signals; noise generated by oscillator operation; and on-chip signal artifacts generated by switched capacitive loads.

Many design techniques can be used to reduce simultaneous switching noise (SSN). Shoot-through current is a major source of SSN. All clock drivers, bus drivers, and output pin drivers can be affected by this effect. This effect occurs in complementary inverters where both the p-channel transistor and the n-channel transistor are turned on simultaneously when the output state changes. Shoot-through current can be minimized by ensuring that the complementary transistor is turned off before the other transistor turns on. In the design of high current drivers, this may require a pre-driver to control the slew rate of the signal at this node.

Cutting off the clock of the modules that are not in use can also reduce SSN. Obviously, this technique is very application-dependent and can improve EMC performance. In highly integrated microcontroller chips such as Motorola's MPC555 and 565, all peripheral modules of the chip have this function.

SSN will also generate radiation interference. The instantaneous power supply and ground current will flow through the device pins to the external decoupling capacitor. If the loop formed by the circuit (including bonding wires, package leads, and PCB lines) is large enough, signal emission will occur. The parasitic inductance in the loop will generate a voltage drop, which will further generate common-mode radiation interference.

The strength of the common mode radiated electric field E is calculated by the following equation:
E = 1.26 x 10-6 Iw fl/d
E = 1.26 x 10-6 Iw fl/d

Here E is in volts/meter, Iw is in amperes, f is in hertz, l is the path length, d is the distance to the path, and l and d are both in meters. In complex designs, the frequency is determined by specific application requirements and cannot be reduced, so SoC design engineers must carefully consider how to reduce the electric field strength by reducing Iw or l.

Taking care of clock domains can also reduce SSN. Many good SoC designs are synchronous circuits, which are prone to large peak currents at the clock edges. Distributing clock drivers throughout the chip instead of using one large driver can spread out transient currents. Another possible approach is to ensure that clocks do not overlap each other. Of course, care must be taken to avoid contention due to timing mismatches. More importantly, clock signals should be kept away from sensitive I/O logic signals, especially analog circuits.

Today's complex embedded MCUs have many output signals, most of which must be able to respond quickly to capacitive loads. These signals include clock, data, address, and high-frequency serial communication signals. For internal nodes, both penetration current and capacitive loads can generate noise. Applying the same techniques to internal nodes can solve the problem of output pin driver circuit noise. In addition, the fast transition of the signal on the pin can generate signal ringing and crosstalk on the output signal line caused by reflections.

There are many solutions to minimize this type of noise source. Output drivers can be designed with controlled drive strength and signal slew rate control circuits can be added to limit di/dt. Since most device test equipment has higher test node capacitance than the end application, it is usually preferred to specify a fixed value to achieve drive strength control. For example, assume that the full drive strength of the CLKOUT of the MPC5XX series MCU microcontroller chip is a 90pF load and is set for test purposes. Except for timing considerations, it is better to use a reduced drive strength.

The techniques described above have a positive effect on reducing noise, as the average current actually increases due to the extension of the transient current envelope. Implementing an LVDS physical layer on the chip can also reduce the noise generated by large transient currents on the output pins, which relies on differential-mode current sources to drive low-impedance external loads (Figure 2). The voltage swing is limited to ±300mV.

The additional pins required to support this technology can be offset by reducing the power pins. Since this implementation effectively reduces the on-chip transient current, the output driver maintains a nearly constant DC current through the power supply, while the transient current in traditional drivers will produce large voltage swings on capacitive loads.

There are two aspects of oscillator design that affect EMC: the shape of the input and output signal waveforms, which have an impact; and the ability to broaden the spectrum and reduce its narrowband power by frequency dithering.

Oscillators are analog in nature and are therefore more sensitive to process, temperature, voltage, and load effects than digital circuits in SoCs. Using feedback in the form of an automatic gain control (AGC) circuit to limit the oscillator signal amplitude can eliminate most of these effects. Another alternative implementation of AGC is a dual-mode oscillator that can switch between high current mode and low current mode. Initially, the high current mode is used when the power is turned on to ensure a short startup time, and then switches to low current mode to ensure minimal noise.

In SoC designs that incorporate a phase-locked loop as part of the oscillator circuit, frequency jittering can be used to vary the clock frequency over a small range, thus reducing the base energy as the frequency is spread over a range. The entire system design must be carefully considered to ensure that the rate of change and the frequency range do not affect the timing of critical devices in the end application. This cannot be done in serial communications such as CAN, asynchronous SCI, and timed I/O functions that are widely used in automobiles. Switching noise on the chip manifests itself as a damped oscillation of the desired signal output, which is the result of the inductance in series with the load capacitance on the chip. For a typical on-chip bus, the load is a long PCB trace connected to many tri-state buffers, and the majority of the load is capacitance, including gate, pn junction, and interconnect capacitance.

Removing the inductor or reducing the di/dt can reduce or eliminate the noise. Only when the noise amplitude is large enough to cause the connection node to switch incorrectly, you need to seriously consider the noise problem in the design.

Reducing sensitivity to external noise sources involves consideration of external components as well as internal design. External transient currents can cause two situations on the pins: voltage changes can cause capacitively coupled currents to enter the device; voltages that exceed the power supply range can eventually conduct currents into the device through resistive paths.

In automotive electronics design, external RC filters are often used to limit transient voltage swings and injection currents. Care must be taken to ensure that external component values ​​take into account leakage current effects, especially for analog inputs. It is worth noting that MCUs and peripheral ICs often have up to 200 I/O pins, and the additional cost and board space required for this solution make engineers reluctant to adopt it in system design. The best solution is to achieve high integration on the chip.

Hardware and software techniques can work together to achieve EMC performance requirements. For example, many MCUs have the ability to output internal accesses on an external bus, which is usually invisible. This is very useful for debugging, but in some improperly designed systems, external bus contention may occur, which increases the associated noise.

In past work I have encountered similar problems with on-chip A/D converters reading incorrect values, and it seemed as if noise was somehow interfering with the measurement or conversion. By looking at the hardware block diagram of the system, it seemed that everything seemed normal on the surface with the input of the A/D converter, but I noticed that the external EPROM was decoded in a way that could cause bus contention in some very specific cases. This contention would not affect any operation of the program, but would generate enough noise to cause occasional errors in the A/D conversion. The problem was quickly solved by changing the decoding logic.