Anti-interference technology and application of single chip microcomputer

introduction

As the application of single-chip microcomputers in various fields becomes more and more extensive, the requirements for their reliability are also getting higher and higher. The reliability of the single-chip microcomputer system is determined by many factors, among which the system's anti-interference performance is an important indicator of reliability. The industrial environment has strong electromagnetic interference, so anti-interference measures must be taken, otherwise it will be difficult to operate stably and reliably.

Interference in industrial environments generally enters the microcomputer system in the form of pulses, and there are three main channels, as shown in Figure 1.

Space interference (field interference), electromagnetic signals enter the system through space radiation.

Process channel interference, interference enters through the forward channel, backward channel connected to the system and the mutual channel with other systems.

The power supply system is disturbed and electromagnetic signals enter the system through the power supply lines.

Generally speaking, spatial interference is much smaller in intensity than the other two types, so in microcomputer systems, the focus should be on preventing interference between process channels and power supply systems.

There are two types of anti-interference measures: hardware measures and software measures. If hardware measures are appropriate, most interference can be kept out, but there will still be a small amount of interference that enters the microcomputer system, so software measures are essential as the second line of defense. Since software anti-interference measures are at the expense of the CPU, if there is no hardware to eliminate most interference, the CPU will be busy and have no time to take care of normal work, which seriously affects the work efficiency and real-time performance of the system. Therefore, a successful anti-interference system is composed of a combination of hardware and software.

The laser marking control system designed by the author has a harsh on-site operating environment and many interference factors, such as AC noise, power grid interference and other electromagnetic interference. Therefore, effective anti-interference measures must be taken to ensure stable operation of the system. The following introduces the anti-interference measures we have taken on the hardware, software and CPU of the system.

Hardware measures

Optical Isolation

It is very beneficial to use photoelectric isolators on the input and output channels to transmit information. It electrically isolates the microcomputer system from various sensors, switches, and actuators, and a large part of the interference will be blocked. The stepper motor drive circuit in this system uses a photoelectric isolator 4N33. The circuit is shown in Figure 2.

Overvoltage protection circuit

An overvoltage protection circuit should be used on the input and output channels to prevent the introduction of high voltage and damage to the microcomputer system. The overvoltage protection circuit is composed of a current limiting resistor and a voltage regulator. The current limiting resistor should be selected appropriately. If it is too large, it will cause signal attenuation, and if it is too small, it will not protect the voltage regulator. The selection of the voltage regulator should also be appropriate. Its voltage regulation value should be slightly higher than the highest transmission signal voltage. If it is too low, it will limit the effective signal and distort the signal. The stepper motor drive circuit uses an overvoltage protection circuit.

Anti-interference power supply

The power supply line of the microcomputer system is the main source of interference. The power supply is connected to the power grid using an isolation transformer to prevent interference from the power grid from invading the microcomputer system. The difference between an isolation transformer and an ordinary transformer is that it adds a shielding layer between the primary and secondary, and grounds it together with the iron core.

Configure decoupling capacitors

In principle, each integrated circuit chip should be equipped with a 0.01mF ceramic capacitor to eliminate most high-frequency interference.

Good grounding

This system has both analog and digital circuits, so the digital ground and analog ground must be separated and finally connected at only one point. If the two are not separated, they will interfere with each other.

Software measures

When the microcontroller outputs a signal, external interference may cause the signal to go wrong. In this system, the signal sent by the microcontroller to drive the stepper motor is latched by the latch and then transmitted to the drive circuit. The latch is very sensitive to interference. When interference occurs on the latch line, it will blindly latch the current data regardless of whether it is valid. Therefore, the latch and the microcontroller should be installed on the same circuit board first, so that the control signal that has been latched is transmitted on the transmission line. In terms of software, the most effective method is to repeatedly output the same signal. As long as the repetition cycle is as short as possible, the latch will not have time to respond effectively after receiving an interference error signal, and a correct output signal will come again, which can prevent the occurrence of erroneous actions in time.

CPU anti-interference measures

The previous anti-interference measures are for I/O channels. The interference has not yet affected the MCU itself. At this time, the MCU can still correctly execute various anti-interference programs. When the interference affects the MCU itself (through interference with the three buses, etc.), the MCU will not be able to execute the program in a normal state, causing confusion. How to detect that the MCU is interfered with, how to intercept the out-of-control program flow, how to reduce the loss of the system, and how to restore the normal operation of the system are the problems that CPU anti-interference needs to solve. We adopted the following methods.

Manual Reset

The easiest way to deal with a runaway CPU is to reset it so that the program automatically starts executing from 0000H. To do this, simply add a high-level signal to the RESET terminal of the microcontroller and keep it for more than 10ms.

Power-off protection

The instantaneous power failure or sudden voltage drop of the power grid will cause the microcomputer system to fall into a chaotic state. After the power grid voltage returns to normal, the microcomputer system is difficult to return to normal. The effective way to deal with this kind of accident is power failure protection. The power failure signal is detected by the hardware circuit and added to the external interrupt input terminal of the microcontroller. The software interrupt defines the power failure interrupt as a high-level interrupt, so that the system can respond to the power failure in time. In the power failure interrupt subroutine, the site protection is first performed to save the important state parameters at that time. When the power returns to normal, the CPU is reset, the site is restored, and the unfinished work is continued.

Sleep disturbance prevention

The CMOS type 51 series microcontroller has a sleep state, in which only the timing/counting system and the interrupt system are in operation. At this time, the CPU will not respond to any interference on the system bus, thus greatly reducing the system's sensitivity to interference.

After careful analysis of the system software, we found that the CPU is often executing some waiting instructions and loop checking programs. Although the CPU has no important work at this time, it is awake and easily disturbed. Let the CPU sleep when it is not working normally, and wake it up by the interrupt system when necessary, and then put it to sleep again. After adopting this arrangement, most CPUs can spend 50~95% of their time sleeping, which greatly reduces the threat of random interference to the CPU and reduces the power consumption of the CPU.

Instruction redundancy

When the CPU is disturbed, it often treats some operands as instruction codes to execute, causing program confusion. At this time, we must first get the program back on track as soon as possible (execute the real instruction series). All instructions in the MCS-51 system do not exceed 3 bytes, and there are many single-byte instructions. When the program jumps to a single-byte instruction, it is automatically put on track. When it jumps to a double-byte or three-byte instruction, it may fall on its operand, and continue to make mistakes. Therefore, we should use more single-byte instructions, and artificially insert some single-byte instructions (NOP) in key places, or repeat the valid single-byte instructions. This is instruction redundancy. [page]

Inserting two NOP instructions after double-byte and three-byte instructions can protect the subsequent instructions from being disassembled. In other words, if two NOP instructions are inserted before a certain instruction, this instruction will not be disassembled by the out-of-control program rushing down from the front, and will be fully executed, so that the program is on the right track. However, too many redundant instructions cannot be added, so as not to significantly reduce the efficiency of normal program operation. Therefore, two NOP instructions are often inserted before some instructions that play a decisive role in the flow of the program to ensure that the flying program is quickly included in the correct control track. Such instructions include: RET, RETI, LCALL, SJMP, JZ, CJNE, etc. Two NOP instructions can also be inserted before some instructions that are critical to the working status of the system (such as SETB EA) to ensure that they are correctly executed. Among the above-mentioned key instructions, RET and RETI themselves are single-word instructions, and they can be used directly to replace NOP instructions, but there may be an increase in potential dangers, which is not as safe as NOP instructions.

Software traps

There are conditions for the instruction redundancy to stabilize the flying program. First, the flying program must fall into the program area, and second, the redundant instruction must be executed. When the flying program falls into the non-program area (such as unused space in EPROM, data table area in the program), the first condition is not met. When the flying program has automatically formed an infinite loop before encountering redundant instructions, the second condition is also not met. The measure taken to deal with the former situation is to set up a software trap, and the measure taken for the latter situation is to establish a program operation monitoring system (WATCHDOG).

The so-called software trap is a guide instruction that forcibly guides the captured program to the program that handles the program error. If we call the entry label of this program ERR, the software trap is an LJMP ERR instruction. In order to enhance its capture effect, two NOP instructions are generally added in front of it. Therefore, the real software trap consists of three instructions:

NOP

NOP

LJIMP ERR

Software traps are placed in the following four locations:

(1) Unused interrupt vector areas. When interference opens unused interrupts and activates them, further confusion will occur. If traps are placed in these areas, erroneous interrupts can be caught in time.

(2) Large unused ROM space. Nowadays, EPROM is rarely used up. The remaining large unprogrammed ROM space is generally kept as it is (0FFH). 0FFH is a single-byte instruction (MOV R7, A) for the instruction system. After the program is ejected to this area, it will flow downstream and will not jump again (unless it is disturbed by new interference). As long as we set a trap every other section, we will be able to capture the ejected program. The software trap must point to the error handling process ERR. We can arrange the ERR word at the beginning of 0030H. No matter how the program is modified, the address of ERR is always fixed after compilation (because the interrupt vector area in front of it is fixed). In this way, we can use 00 00 02 00 30 five bytes as traps to fill the unused space in the ROM, or set a trap every other section (02 00 30), and keep the other units unchanged at 0FFH.

(3) Tables. There are two types of tables. One is a data table, which is used by the MOVC A, @A+PC instruction or the MOVC A, @A+DPTR instruction. Its content is not an instruction at all. The other is a scattered transfer table, which is used by the JMP @A+DPTR instruction. Its content is a series of three-byte instructions LJMP or two-byte instructions AJMP. Since the table content and the search value have a one-to-one correspondence, arranging a trap in the middle of the table will destroy its continuity and correspondence. Only a five-byte trap (NOP NOP LJMP ERR) can be arranged at the end of the table.

(4) Program area. The program area is composed of a series of execution instructions. There are often some breakpoints between these instruction strings. The normally executed program will not continue to execute at this point. Such instructions include JMP, RET, etc. At this time, the value of PC should jump normally. If it continues to execute in sequence, it will inevitably go wrong. Of course, if the program that pops up happens to fall on the operand of the breakpoint or the operand of the previous instruction (and no redundant instructions are used before this instruction), the program will skip the breakpoint and continue to rush forward. After we arrange a trap in this place, we can effectively capture it without affecting the normal execution of the program flow. For example:

…

AJMP ABC

NOP

NOP

LJMP ERR

…

ABC: MOV A, R2

RET

NOP

NOP

LJMP ERR

ERR: ...

Since software traps are placed in places where the program cannot be executed normally, they will not affect the efficiency of program execution.

Conclusion

In summary, by comprehensively considering the software and hardware of the single-chip microcomputer application system and taking different technical measures for different situations, the system is guaranteed to operate accurately and reliably. After the laser marking control system adopts the above anti-interference measures, the system reliability is greatly enhanced, the operation is stable, and the effect is ideal. It has now been mass-produced and has achieved good economic benefits. ■

References

1. Chen Guangdong, Zhao Xingchu, Principles and Interface Technology of Single-Chip Microcomputers, Huazhong University of Science and Technology Press, 1995: 150.

2. Shao Beibei, Reliability technology and development of single-chip microcomputer system, Electronic Products World, 1998;8:20-21.