Zigbee sensor node hardware design based on single chip microcomputer

introduction

ZigBee Alliance defines two types of physical devices: one is full function device FFD (full function device); the other is reduced function device RFD (reduced function device). The construction of the network requires the participation of the coordinator (FFD). The entire network formation process: first initialize, then the coordinator starts to participate in the establishment of the network, and after the network is established, the router (FFD) and the terminal device (RFD) discover the network, and finally start data management and transmission in the established network.

1 Node Hardware Design

The sensor node is composed of several different modules, which handle different functions. There is a sensor module, which is the hardware basis of sensing, followed by a processor module, which performs important functions. Communication can only be carried out after data processing, as well as a wireless communication module and an energy supply module. The main functions of the sensor node are: first, data collection of the data node, then processing of the collected data, and then forwarding of the processed data through the node for fusion. At the same time, other nodes forward data, so that the data of all nodes are managed and fused, and the data is stored after processing. The working principle and structure of all sensors are roughly the same. Although each sensor design is different, the basic architecture is the same. This function of the sensor node is equivalent to the routing function of the traditional network. As a network terminal to transmit and receive data, it is the basis for the formation of the five networks. The basic element of the wired network is the sensor node, and the node is the basic platform for the formation of the wireless sensor network.

Since traditional nodes are used to collect data, not only the number of nodes is large, but also the working time is long and the efficiency is low, this design has made some improvements. The hardware design adopted this time integrates the characteristics of different hardware. The processor is the AVR microcontroller ATmega128L processor, which has the characteristics of high performance, fast speed, and low power consumption. Compared with ordinary 8-bit machines, it is more practical and has rich hardware resources. It has the characteristics of high performance, high speed, low power consumption and rich hardware resources.

The CPU has several power saving modes: IDLE, POWERSAVE, POWERDOWM, STANDYBY. It can work efficiently in different power saving modes. The clock control is provided by an 8MHz crystal oscillator, and the clock frequency can be changed and selected by software. The internal integrated program memory size is 128KB, there is also 4KB static RAM, and it has 4KB E2PROM.

1.1 Communication Module

CC2420 is a low-power communication chip developed by Chipcon. It is characterized by short delay time, which allows more sufficient sleep time. Maintaining this state can not only improve efficiency and save energy, but also prolong the service life of the node. CC2420 is easy to connect to the processor, and four pins are used to indicate the state of the data, which use SFD, FIFO, FIFOP and CCA respectively. The interface uses the SPI interface, which exchanges data and sends commands with CC2420. When reset, it enables and resets through the VREG_EN and RESET_N2 pins, generates an operating voltage that matches CC2420, which is generally 1.8V, to ensure that the processor enters a normal working state. Since the pins connected to the antenna have high impedance characteristics, the pins are RF_P and RF_N. High impedance matching requires a high impedance antenna, and the matching load impedance is generally required to be 115+j×180.

1.2 Memory section

This design uses the Flash memory chip AT45DB041 with a serial interface. It has a storage space of 4Mbit and can be easily connected to the serial port. Since a network sensor node has two functions, router and host, the on-chip storage unit of the processor ATmega128L cannot meet the requirements, so it must be expanded accordingly. Each node must have an independent serial number. This design chooses the DS2410Z serial number memory. It has a 64-bit ROM, which contains a 48-bit unique serial code, an 8-bit CRC check code and an 8-bit family code. The data uses the 1-Wire protocol, does not require external power supply, and is transmitted serially only through 1 signal lead and 1 ground loop. The routing function uses the Flash memory chip AT45DB041 with a serial interface. It has a storage space of 4Mbit and can be easily connected to the serial port of ATmega128L.

1.3 Other modules

The design uses a photosensitive sensor, and the power module is powered by two 1.5V dry batteries. The choice of sensor modules is relatively flexible, and different sensors can be selected according to actual conditions. The node design processor is in power saving mode, and the RF module is in sleep mode when there is no task, so as to minimize the power consumption of the node.

1.4 Design points

In order to reduce the interference of peripheral signals, the signal line and ground line must be separated and divided into several levels, and an independent module design is adopted. Considering the design points of more streamlined volume and the need to reduce signal interference, a multi-layer board can be used. In the high-frequency working state, the area of ​​​​this layer that is not used for wiring must be filled with copper and connected to the ground.

2. Software Design of Node Machine

The development software used in this article is the integrated development environment of WinAVR20050214 version and the AVRStudio4 download program. The software modules mainly include: CC2420 driver, network routing design, etc. [page]

2.1 Coordinator Software Design

The software flow chart of the coordinator is shown in Figure 1. When the system is just initialized, the hardware protocol starts to establish a network after initialization, determines whether the node is connected to the network, runs the protocol task after successful access to the network, receives the node data and sends it to the PC.

If the number of times is exceeded during the establishment process, the reception fails and the next reception will be continued.

Figure 1 Coordinator software flow

2.2 Software Design of Member Nodes

The member nodes mainly collect sensor data and receive control data from the coordinator. When there is no data to be sent or received, they enter the sleep state, and the node power consumption is reduced to the minimum. The software design flow chart of the member node is shown in Figure 2. After the system is initialized, the hardware and protocol are initialized. After the successful loading, the protocol task is performed. After the task is judged, the sensor data is measured and sent to the coordinator. After entering the sleep state, the next task is executed. If the specified number of times is exceeded, the network establishment fails.

Figure 2: Software flow of member nodes

2.3 Design of Physical Layer and MAC Layer

The CC2420 chip provides data services and management services at the physical layer. The service interface of the MAC layer point-to-point communication completes the transmission and reception of sensor data through program control of the CC2420 register. The MAC frame format defined by IEEE802.15.4: MAC layer header frame; MAC payload; MAC layer frame tail. Among them, MHR has a fixed order, and not all frames contain the address field.

2.4 Network Layer Design

You can choose AODV routing or tree routing according to the actual situation.

The network layer of ZigBee supports a variety of network topologies, and a star network is selected to limit the number of nodes. In a star network, nodes are configured as one full-function node and one or more simplified function nodes, and all RFDs can only communicate with FFDs. The network layer protocol of the node adopts a routing algorithm that combines the tree routing algorithm with the AODV routing algorithm. The tree routing algorithm refers to the use of a tree structure address when making a routing selection strategy; the AODV algorithm is an improvement on the AdHoc on-demand distance vector routing algorithm. This article designs a star network for node networking test, one of which is a coordinator and the other two are light sensor nodes. From the visualization background software SNAMP, you can see the network topology composed of nodes and the received data packets, as shown in Figure 3.

Figure 3 Node hardware physical picture and network test

3 Conclusion

Through this design, the experiment proved that the node is small in size, highly integrated, and has low power consumption. The multi-level wiring not only reduces signal interference, but also increases the transmission distance. The software design can realize the transmission of coordinators, routers, and network terminals through node programming. The module design in the hardware can change different sensor modules according to specific needs, which has higher flexibility.