Design of high-speed digital signal processing board based on PCI interface

With the improvement of the performance of digital signal processors (DSP) and their peripheral support chips, software radio has been widely used, greatly enhancing the overall performance of real-time signal processing systems. On the other hand, as ADC and DAC move forward to the RF direction, the sampling frequency of the signal is also increased accordingly, which makes the bandwidth of DSP system data exchange increase exponentially. The bottleneck effect of traditional data exchange interfaces is becoming more and more obvious, so a number of new interface standards have been born accordingly. Since the PCI interface was proposed in 1993, it has been supported by many computer equipment manufacturers and has been widely used in related fields such as PCs and industrial control.

Passive radar is a device that uses the signal emitted by a non-cooperative external radiation source as a detection signal (such as broadcast signals, TV signals, GSM mobile phone base station signals, etc.) to extract the target's azimuth, speed and other parameters from the echo signal reflected by the receiving target. Compared with traditional radars, it is passively received, so it has strong concealment. After the emergence of stealth aircraft, passive radar technology has received widespread attention. Because stealth aircraft introduce special microwave absorbing materials and adopt a special appearance design, it is difficult for traditional single-base millimeter-wave radars to detect it. The detection signal used by passive radar is the radio and television signal. Since the wavelength of radio and television signals is within the range of meter waves, the microwave absorption materials designed for millimeter wave wavelengths are ineffective. In addition, in the configuration of the transceiver station, since the passive radar is designed to work as a dual-station or multi-station system, it also destroys the design idea of ​​stealth aircraft to blank the electromagnetic wave signal transmitted in the same direction of the transceiver. Therefore, passive radar is becoming a powerful weapon against stealth aircraft. This paper focuses on the application of passive positioning radar signal processor, and uses the PCI interface to realize the rapid and real-time transmission of DSP processing results to the PC, which completes the functions of data fusion and display recording.

1 Design of high-speed signal processing board based on PCI interface

Figure 1 is the principle block diagram of the board. The intermediate frequency (30MHz) narrowband (bandwidth is 30MHz) narrowband (bandwidth is 200kHz) orthogonal signals output by the passive radar receiver are buffered and filtered before being sent to the A/D converter AD9051 for high-speed analog-to-digital conversion. The use of direct intermediate frequency bandpass sampling not only reduces the complexity of the receiver, but also reduces the output noise level of the receiver, which is beneficial to improving the sensitivity and dynamic range of the receiver. With a sampling frequency of 30MHz, the data stream first enters the FIFO memory IDT72V255 cache. When the FIFO is full, the EPLD (EMP7128) gives the TMS3206701 DSP an external interrupt signal to start the DSP's DMA transfer and quickly transfer the data in the FIFO to the synchronous burst static memory (samsung K7A163601M) outside the DSP chip. After the DMA transfer is completed, the DSP performs time-space two-dimensional correlation processing on the sampled data [1], and the processing results are first written into the dual-port RAM (IDT70V25). The data exchange between the PCI bus and the dual-port RAM is carried out in the form of a mailbox register (Mail Box). The specific implementation is as follows: first, a storage unit is defined at a fixed address in the dual-port RAM as the "mailbox" for communication between the two parties. This storage unit is called the mailbox register. The initiator of the data communication first checks whether the mailbox register is empty. If the mailbox register is empty, the data is written to the dual-port RAM; otherwise, it waits for the mailbox register to be empty. The receiver of the data continuously queries the mailbox register. If it is found that the value of the mailbox register is not empty, the data in the dual-port RAM is read in, and the mail register is set to an empty value. The advantage of using this method is that the exchange of bidirectional data streams can be completed directly without the need for external data communication handshake signals and logic. It is very suitable for transmission with long communication repetition intervals and large data blocks.


2 PCI interface design

In the second half of 1991, Intel first proposed the concept of PCI bus, and jointly with more than 100 companies such as IBM, Compaq, AST, HP, DEC, etc., launched the PC local bus standard - PCI bus in 1993. PCI is a set of overall system solutions, which is superior to other local buses that are only used to accelerate graphics or video operations. The PCI local bus uses a 32-bit or 64-bit data bus, operates at a clock frequency of 33MHz or 66MHz, and can support multiple sets of peripheral components and add-on cards. At 33MHz, its data transfer rate is as high as 132MB/s; at 66MHz, its data transfer rate doubles. In addition, it supports linear burst data transmission mode to ensure that the bus is constantly fully loaded with data. Peripheral devices generally receive data sequentially from a certain address in the memory, which means that a large amount of data can be read and written from one address, and then the address only needs to be automatically increased by 1 each time to receive the next byte of data in the data stream. Linear burst transmission can more effectively utilize the bus bandwidth to transmit data to reduce unnecessary address operations. In radar signal processing, the real-time requirements of the signal are very high, which requires that the bandwidth of signal transmission should be high enough. The PCI interface is very suitable for bridging high-speed signal processing modules and computers. At present, the design of PCI interface generally adopts two methods: one is to use a universal interface chip. Commonly used chips include: AMCC's S5933, PLX's PLX9054, etc. The second is to use EPLD or FPGA. This method can customize certain functions according to its own needs, so the design flexibility is large, but the PCI bus specifications must be strictly followed. The advantage of using a universal interface chip is that you don't have to worry about PCI bus operations during design, as long as you handle the local bus interface. The design is simple and time-saving. This article uses the C mode of PLX9054 to complete the PCI interface function. PLX9054 has an independent local bus (Local Bus), which is responsible for access control of dual-port RAM.


3 EPLD control timing implementation

EPLD uses Altera's EMP7128S to complete ADC sampling control, FIFO read and write control, sampling end interrupt generation and other functions. The MAXPLUS II integrated development environment software provided by Altera is used, which supports VHDL, Verilog HDL and AHDL languages. In addition, it also supports the direct input of schematic diagrams. This article is written in AHDL language. Figure 2 is a simulation timing diagram, where CLK is the input external clock signal, WR is the write signal of FIFO, ENCODE is the sampling clock signal of ADC, TR is the sampling trigger signal, and INT is the output interrupt signal. COUNT is a data sampling length counter. Although FIFO can provide full and half full flags, using this as the interrupt generation condition limits the flexibility of the sampling length. In order to customize the sampling length in the application and realize the sampling of data of any size (maximum not exceeding the storage depth of FIFO), the sampling length counter is introduced in the design. As long as the initial count value of COUNT is properly set (the size is the complement of the sampling length), the INT interrupt signal is given when the counter overflows, this function can be realized. The ADC uses AD9051, which uses a 5-stage pipeline structure to output data. When sampling is just started, the pipeline is not full, so the first 5 data output are invalid. The A/D conversion results are stored in the FIFO from the 6th data. [page]


4 SBSRAM interface design

SBSRAM is synchronous burst static memory. Its biggest advantage is high read and write speed and no need for refresh. In burst mode, as long as the external device gives the first access address, the rising edge of the synchronous clock can generate a burst address for accessing the data unit internally, helping controllers that cannot quickly provide access addresses to speed up data access. Since the EMIF (Extended Memory Interface) of TMS320C6701 can provide addresses at the speed of SBSRAM, the burst mode of SBSRAM should be disabled (/ADV connected to a high level). However, this does not mean that the read and write performance will be reduced. In fact, since the DSP can continuously output new addresses and control commands in each data access cycle, it can still achieve the peak read and write speed in burst mode. Since the synchronous clock frequency for accessing SBSRAM is 80MHz, the quality of high-speed digital signal transmission on the circuit board is particularly important [2].

When designing PCB, signal integrity (SI) must be taken seriously. It mainly includes reflection, ringing, ground bounce, crosstalk, etc. In the past, high-speed PCB design required high user experience. Now, with the help of EDA auxiliary software, signal integrity problems can be foreseen in the design and certain measures can be taken to control them. According to the selected PCB substrate (dielectric constant, board thickness), it is easy to calculate the impedance of the transmission line using the free software AppCAD provided by Agilent, and then calculate the best termination matching resistance.

After completing the PCB design, the design can be verified using the BoardSim function of HyperLynx. BoardSim uses the popular IBIS model (Input/Output Buffer Information Specification). When simulating, the IBIS model of the device should be loaded into the specified port first, the clock frequency should be set equal to the operating frequency of the system, the probe of the oscilloscope should be connected, and the simulation results can be seen after starting the simulation. Figure 3 is the simulation waveform without the termination resistor. It can be seen that the signal quality is very poor, and the ringing and overshoot phenomena are serious. Figure 4 is the simulation waveform with 33Ω serial resistor termination. The ringing and overshoot phenomena have been greatly improved, and the signal quality is better.

5 DSP signal processing flow

The DSP signal processing algorithm is mainly based on references [1] and [3], and performs two-dimensional correlation operations on the signal in time and frequency. The peak value in the time dimension can be used to calculate the distance of the target, and the peak value in the frequency dimension can be used to calculate the speed of the target. The signal processing flow is shown in Figure 5.

Applying the PCI interface to the DSP system speeds up data transmission, and can fully utilize the rich software and hardware resources on the PC platform to complete tasks such as data fusion, target display, and parameter setting. The DSP chip is assigned to tasks with large computational load and strong real-time performance, making full use of the strengths of the DSP chip, thus realizing the complementary advantages of the PC and DSP systems. The organic combination of the two can build a signal processing system with strong real-time performance, friendly interface, and convenient operation.