Interface Design between Serial D/A Converter and Single Chip Microcomputer

1 Introduction

MAX521 is a 2-wire 8-channel 8-bit voltage output DAC (digital-to-analog converter). MAX521 has 5 reference voltage inputs. The first four DACs (DAC0 to DAC3) each have an independent reference voltage input (REF0 to REF3), allowing the voltage range of each channel to be set independently; the remaining four DACs (DAC4 to DAC7) share a reference voltage input REF4. It has a serial interface and built-in software protocol, allowing the maximum conversion frequency to reach 400kbps. The interface of MAX521 has a double-buffered input structure, allowing the DAC registers to be updated individually or simultaneously; it has a low-power mode that can reduce the operating current to 4μA. MAX521 is powered by a single +5V power supply.

Applications: Minimum analog device systems; Data offset/sampling adjustment; Industrial process control; Automatic detection equipment.

MAX521 has three package types: 20-pin DIP, 24-pin SO and 24-pin SSOP. The pinout of 20-pin DIPMAX521 is shown in Figure 1.

OUT0~OUT7: voltage output of DAC0~7; REF0~REF3: reference voltage input of DAC0~3; REF4: reference voltage input of DAC4~7; AD0, AD1: device address input pins; SCL: serial clock input; SDA: serial data input; DGND: digital signal ground; AGND: analog signal ground

2MAX521 software communication protocol

I2C bus composition: It consists of only two lines. One is the clock line (SCL) and the other is the data line (SDA). The SCL line is a clock signal, generated by the bus control device, providing a unified clock signal for the bus.

The SDA line is a data signal that is transmitted bidirectionally between the bus control device and other devices on the bus.

The I2C bus protocol stipulates that the SDA signal is valid when SCL is high, and data changes on the SDA line should be performed when SCL is low. The only exceptions to this rule are the start signal and the stop signal.

The format of I2C input/output of a byte is high bit first, low bit last. Each I2C bus access is composed of a series of basic operations, which are explained in detail below.

2.1 Start signal

Before each I2C bus access, a start signal must be sent on the bus. When the SCL line is high, the SDA line changes from high to low, forming a start signal.

2.2 End signal

After each I2C bus access, an end signal is sent on the bus. When the SCL line is high, the SDA line changes from low to high, forming an end signal.

The timing diagram of the start signal and the stop signal is as follows:

2.3 Device addressing byte

Both read and write operations require a device address byte. The first five bits of the MAX521 address byte are 01010 (the device flag code). The last two bits are the device address, which is determined by the state of the AD0 and AD1 pins of the MAX521. The last bit X is used to write or read data to the device. If data is written to the MAX521, X is 0. [page]

Below is the complete working timing diagram of MAX521:

2.4 Data address byte or command byte

The device addressing byte is followed by the command word. The first three bits of the command word are 0, the next two bits are RST and PD, and the next three bits A2A1A0 are the channel addresses of the 8 DAC output registers. The working sequence of the data address byte or command byte is shown in Figure 4:

R2R1R0 is set to 0 and is a reserved bit. When RST is high, MAX521 resets all DAC registers, but the output remains until the "stop" signal. When the PD bit is high, MAX521 enters low-power mode after receiving the "stop signal". In low-power mode, the DAC output depends on the channel address setting and output byte setting status at this time, and the maximum current provided is 20μA. When the PD bit is low, MAX521 returns to normal working state and then sends a "stop signal". The voltage of the DAC output depends on the current channel address setting and output byte setting.

2.5 Response signal

During the ninth clock pulse after each address byte or data byte is transmitted, the receiver generates a low-level ACK signal on the SDA line to notify the sender that the data has been received and can continue to be sent. After all data has been transmitted, the microcontroller sends a stop signal to the SDA line to end the data transmission.

Notice:

1) When the bus is idle, the SCL and SDA lines should remain high.

2) Before a new start, the bus idle time tBUF>4.7μs.

3) The time when the clock is high and low, the time to establish the start signal, and the time to establish the end signal must all be greater than 4.7μs.

4) The time interval between two write transmissions is tWR＞10ms.

5) The operating rate of the SCL line can reach 400kHz.

3MAX521 and MCU interface and program

As shown in Figure 1, MAX521 is connected to P1.6 and P1.7 of the microcontroller and used as an I2C bus. All reference voltages are connected to +5V, so that the output analog voltage value is between 0 and +5V. The device address is set to 01B. The execution device is connected after OUTPUT.

4 Conclusion

This system has been successfully applied in circuits with multiple DAC conversions, which is more energy-efficient than conventional parallel DAC devices and provides a good solution for the development of intelligent equipment.