Using MSP430 to implement Blackfin DSP program boot

Blackfin processor is a series of DSP products jointly launched by ADI and Intel in April 2003. It is mainly aimed at embedded audio, video and communication fields. In addition to powerful signal processing performance and ideal power efficiency, it also integrates 32-bit RISC reduced instruction set. ADSP-BF533 is the highest performance model in the current Blackfin series of digital signal processors, with a main frequency of 600MHz, dual 16-bit MAC (multiplier and adder) and two 40-bit ALU (arithmetic logic unit), 4 8-bit video processing units, 8 arithmetic registers, and 10 address addressing units. DSP integrates 148K bytes of on-chip RAM and has a variety of external interfaces, such as SDRAM, general parallel data port, SPI, PPI, synchronous and asynchronous serial port, etc.

MSP430F149 is an industrial-grade flash memory 16-bit RISC MCU with the characteristics of extremely low power consumption and rich on-chip resources. It is also very suitable for handheld devices.

This system is a software radio handheld device platform, which adopts the dual processor mode of BF533+MSP430F149: BF533 mainly completes the fast capture, tracking and decoding functions of broadband spread spectrum signals; the functions completed by MSP430 include USB controller interface, RF control and DSP guidance, monitoring, etc., as shown in Figure 1.

Figure 1 System structure diagram

MSP430 establishes communication with PC through USB controller, and the whole system is accessed by PC as a USB device. The antenna receives the RF signal and directly down-converts it, and then enters BF533 after AD conversion. The DSP program is stored in the FLASH ROM on the MSP430F149 chip.

MSP430F149 and BF533 are connected via SPI bus, which not only solves the DSP program boot problem, but also realizes the real-time monitoring of DSP.

Blackfin Application Bootstrap Process

The general process of developing a Blackfin application is shown in Figure 2.

Figure 2 Blackfin boot file generation process

DSP application programming and debugging are usually completed in VisualDSP++, an integrated development environment of ADI. During the software design phase, the hardware emulator Summit ICE can be used to connect to the target processor through JTAG (boundary scan test interface) for debugging and development. VisualDSP++ will compile the user application code to generate a DSP executable file (.DXE) and load it into the memory of the target processor through the JTAG port. When designing an independent target system, the boot mode of the user program and the corresponding external memory must be considered. VisualDSP++ generates a boot file (.LDR) corresponding to the memory type and burns the boot file into the external memory. Finally, the boot file is loaded into the DSP memory and executed through a certain boot mode.

BF533 has a fixed boot program (Boot ROM) inside, see Figure 3. After hardware reset, it enters the boot process and executes the boot program stored in the Boot ROM. First, by sampling the two dedicated boot mode selection pins BMODE[1:0], it determines how BF533 will load the user application code/data. Then, the application is booted and executed in the format selected by the user.

Figure 3 Blackfin application boot process [page]

BF533 has 4 program boot modes. Table 1 shows the relationship between the value of pin BMODE[1:0] and the boot mode.

For any mode, the boot program will first read out a 10-byte file header according to the type of external program memory selected by the mode pin. The file header consists of a 4-byte destination address, a 4-byte number of transmitted data (bytes), and a 2-byte control flag. If the user program or data needs to be placed in different address blocks of the DSP memory, the block boot method can be used to load the data, and each block is described by a different file header. Once all blocks are loaded, the processor will end the boot process and start executing the user code placed here from the starting address of the L1 instruction memory (0xFFA00000). The control flags in the file header describe some properties of the block. Figure 4 shows the data flow and file header format during booting.

Figure 4 BF533 boot data stream and file header format

SPI Boot Timing

The SPI bus consists of three signal lines: serial clock (SCLK), serial data output (SDO), and serial data input (SDI). The SPI bus can connect multiple SPI devices to each other. The SPI device that provides the SPI serial clock is the SPI host or master device (Master), and the other devices are SPI slaves or slave devices (Slave). Connect the serial clock pins of each device together, connect the data output of the master device to the data input MOSI (Master Out Slave In) of the slave device, and connect the data input of the slave device to the data output MISO (Master In Slave Out) of the master device.

Since the SPI ports of MSP430 and BF533 can be configured as master or slave devices by software, the same connection method can be used to make both BF533 and MSP430 the host.

When the program is booting, BF533 is the host and the serial clock is provided by BF533. During the monitoring process, MSP430 is the host and controls BF533 through the SPI port. Compared with the booting process, the hardware connection has not changed, except that MSP430 and BF533 each provide a general IO pin for handshake signal to prevent MSP430 from interrupting DSP when DSP is busy.

In this system, the BF533 boot mode is set to boot from a 16-bit serial SPI memory. After the BF533 is powered on or hardware reset, the SPI interface defaults to the master mode and provides a serial clock with a frequency of 500KHz. The first few cycles of the boot sequence are: starting from the first SPI clock cycle, the BF533 generates a read SPI serial EEPROM command byte on the MOSI pin, and its value is 0x03. This value is a read memory command for the SPI serial EEPROM. The memory should send the data in the memory serially to the MISO pin of the BF533 starting from the next clock beat. As shown in Figure 4, the first thing to be sent should be the destination address information 0xFFA00000 of block 1. After reading this value, the DSP will judge the value internally. If the destination address is not a valid address in the DSP memory area, the BF533 will repeat the process of sending the read SPI EEPROM command byte and judging the address validity. If the read address is valid, the memory read sequence will be started and a read SPI serial EEPROM command byte will be sent: first read the file header and then read the boot content.

The MSP430 software should be specially considered in the design to ensure that the boot timing generated by the SPI interface of the MSP430F149 is the same as the timing when booting from the EEPROM. According to the author's development experience, the official version of the BF53x series has the same SPI boot timing, but the SPI timing of the test version chip is different from the official version.

DSP real-time monitoring and online program upgrade

When the DSP program is running, we usually need to know its running status. Therefore, it is necessary to establish a mechanism to realize real-time reading and writing operations on the DSP memory area, that is, to complete real-time monitoring of the program.

In the BF533 application design, the SPI port of BF533 is set to slave mode. After the boot is completed, the SPI port of MSP430 is set to master mode, and the booted BF533 user application starts to execute, thus establishing master-slave SPI communication between MSP430 and BF533.

In addition, the MSP430 is connected to the PC through the USB interface device PDIUSBD12. The monitoring command is initiated by the PC or keyboard operation, and the MSP430 responds to the command sent by the PC through the USB bus or keyboard command, and then operates according to the command type. The monitoring commands are divided into two categories:

(1) PC or keyboard control commands to MSP430. Commands are transmitted to MSP430 through USB bus or keyboard, and MSP430 responds to commands and performs corresponding operations. Such commands include: upgrading DSP program, downloading data to FLASH, peripheral control, etc.

(2) Control commands from PC or keyboard to DSP. This type of command can be sent from PC to MSP430 through USB bus or keyboard operation, or it can be directly initiated by MSP430, and the command recipient is DSP. There are two main types of commands: read DSP memory area and write DSP memory area. The command consists of command packet and data packet. The read command packet mainly includes command code, destination address, read length and check word. After sending the read command packet, if the DSP receives a correct response, the data packet corresponding to the read length is sent. Each data packet sent will receive a packet of data returned by DSP. The write command packet mainly includes command code, destination address, write length and check word. After sending the write command packet, if the DSP receives a correct response, the data to be written is packaged and sent out. If the write is successful, the DSP will receive a correct response.

MSP430 has 60K bytes of on-chip FLASH program memory. In addition to the program space occupied by its own program, it can also free up about 48K bytes of space. In this system, this free space is used to store the DSP program to be booted. The FLASH memory of MSP430 has segmented erasing and programming functions, and the minimum erasing unit is 512 (0x200) bytes. In addition to being able to be programmed with special development tools, its FLASH ROM can also be self-programmed to achieve online upgrades of DSP programs.

Conclusion

The MSP430F149 is used to directly guide the ADSP-BF533 and monitor it in real time. Compared with the usual use of serial EEPROM for booting, this avoids the intermediate process of burning EEPROM and reduces the circuit complexity. The same circuit connection realizes both the booting function and the monitoring function. In addition, through the flexible software programming of MSP430, the system also has the characteristics of flexible control of the booting time and online upgrade of the DSP program.