Wireless RF transceiver system hardware design

0 Introduction

With the rapid development of electronic and computer technology, radio frequency technology, as a wireless network communication method, has been used in more and more occasions and has shown its unique advantages. It replaces the traditional complicated cables, making mobile phones, portable computers, printers, copiers, keyboards and other devices in homes or offices interconnected, freeing people from countless connection cables and freely and conveniently forming their own personal networks. As a short-range wireless communication technology that replaces data cables, it connects various data and voice devices in homes or offices into a micro-network, and can further realize interconnection to form a distributed network, thereby achieving fast and convenient communication between these connected devices. Therefore, it has great development potential in wireless network systems.

1 System hardware composition and working principle

The RF and digital baseband circuits are connected in a suitable way to form the hardware circuit of the designed wireless RF transceiver application system. The overall circuit is shown in Figure 1. Among them, the arrows indicate the connection of external voltage to ensure the normal operation of the circuit. Its working voltage is 3 V.

1.1 System main circuit structure and principle

The RF circuit is mainly designed as a RF transceiver using the TRF6900 transceiver chip and some peripheral components. TRF6900 is a single-chip RF transceiver chip launched by Texas Instruments, which integrates complete transmitting and receiving circuits. Its operating frequency range is 850-950 MHz, the power supply voltage range is 2.2-3.6 V, the RF output power is as high as +5 dBm, and the current consumption in standby mode is only between 0.5 and 5 μA. TRF6900 adopts a high-throughput 16 bRISC structure, and its fastest rate can reach 8 MIPS. In addition, this transceiver also has FM/FSK modulation mode and uses a three-wire serial interface, so it can be easily connected to a microcontroller and can be used for two-way wireless transmission of data in the ISM frequency band. It can easily control its transmission and reception, so its applications are becoming more and more common.

1.1.1 Receiving principle

The signal received from the antenna is introduced into the TRF6900 by LNA IN and first passes through the low noise amplifier. The low noise amplifier provides a gain of 13 dB. It has two modes: normal and low gain. When the signal received by the TRF6900 is strong, the low gain mode should be selected to minimize the nonlinear distortion of the signal. The amplified signal is sent to the mixer, which converts the signal to the intermediate frequency and then amplifies it through the first and second intermediate frequency stages. The first intermediate frequency amplification can obtain a gain of 7 dB to compensate for the loss caused by the filter; the second intermediate frequency amplification includes multiple amplifiers, which can obtain a total gain of 80 dB. After the two-stage amplification, if the FM/FSK modulation method is used, the signal is sent to the FM/FSK demodulator, and the demodulated data signal is led out from DATA OUT. If it is frequency shift keying (ASK) or on-off keying (OOK), it is sent to the received signal strength indicator (RSSI) for demodulation, and the demodulated baseband data is output from RSSI OUT.

1.1.2 Transmission working principle

The digital baseband signal is introduced into the TRF6900 chip from TX DATA, modulated to the intermediate frequency by the direct digital frequency synthesizer (DDS), then multiplied to the radio frequency by the phase-locked loop (PLL), and finally amplified by the power amplifier. The radio frequency signal is derived from PA OUT and then transmitted through the antenna.

1.1.3 Working principle of serial control interface

The serial control interface includes three parts: CLOCK, DATA, and STOBE, which control all registers inside the TRF6900, including the DDS parameter setting register and other control registers. At each rising edge of CLOCK, the logic value of the DATA pin is sent to the 24b shift register, and when the STOBE level is raised, the set parameters are sent to the selected latch. TRF6900 has four programmable 24b control words (A, B, C, D). Control words A and B control the output signal frequency in DDS mode 0 and mode 1 respectively. Control word C is responsible for the setting of the phase-locked loop and DDS mode O. Control word D is responsible for the setting of modulation and DDS mode 1.

1.2 Digital baseband part

The digital baseband part is based on the microcontroller MSP430F1121. It converts the external analog signal into a digital signal suitable for TRF6900, and with the software design, it can easily perform intelligent conversion. The hardware circuit of the digital baseband part consists of RS 232 and MSP430F1121, as shown in Figure 1.

The MSP430F112l microcontroller is an ultra-low power, high-performance 16-bit reduced instruction set MCU, mainly composed of the following parts: basic clock module, including 1 digital control oscillator (DCO) and 1 crystal oscillator; Watchdog Timer Watchdog Timer, which can be used as a general timer; 16-bit timer Timer_A with 3 capture/compare registers; 2 8-bit parallel ports with interrupt function: P1 and P2; analog comparator Comparator A. [page]

2 System parameter calculation

2.1 Reference frequency of phase detector

The phase detector is one of the unit modules in the phase-locked loop of PPL. Its input reference frequency is determined by the output signal of DDS. The frequency synthesizer based on DSS technology can well meet various performance indicators and also make the design simple. The resolution of the phase detector output frequency is:

Where: fpd is the minimum input frequency of the phase detector, which is also 2° of the DDS clock frequency fref, that is, the weight of the least significant bit. The TRF6900 DDS accumulator has 24 bits, and fpd is multiplied by the pre-scaled value N (which can be selected as 256 or 512), from which the minimum frequency step value can be obtained:

The input of the accumulator is 24-bit user serial data (control word), and the clock reference signal is used as the working clock signal of the accumulator. The two determine the frequency resolution; the output is a series of sampled ramp digital pulses, and the number frequency is equal to the clock frequency. After D/A conversion, the analog domain sinusoidal signal fo_DSS is obtained, which represents the reference phase, that is, the reference input signal of the phase detector. The final performance of DDS mainly depends on the quantization error and filtering characteristics in the D/A conversion process.

2.2 Crystal Oscillator Clock Circuit and Frequency

2.2.1 Clock circuit design and parameter calculation

The crystal oscillator adopts parallel resonance working mode, as shown in the peripheral circuit of pins 23-24 in Figure 1. The total phase shift of the circuit is 360°, of which the inverter provides a 180° phase shift, R7 and C22 provide a 90° lag phase, and the crystal oscillator and capacitor C1 also bring a 90° phase lag. The crystal oscillator working in parallel is used as an inductor. The crystal oscillator is connected to a capacitor to compensate for the phase shift to meet the oscillation conditions.

Polarization resistor R1 is used to set the bias point of the inverter. The typical value is half of the Vcc pin value. If R1 is too small, the loop gain will be reduced and the network feedback condition will be destroyed. The typical value is 1 to 5 MΩ. The output frequency of pin 23 can be observed as the voltage changes. If the crystal oscillator is overdriven, the output frequency will decrease after increasing the voltage. At this time, the resistor R2 should be fine-tuned (increased). Note that R2 should be small enough to ensure that the oscillator can start when the voltage is less than the minimum operating voltage. C1, the bypass capacitor Co of the crystal oscillator, and the input capacitor of the inverter together constitute the input capacitance of the crystal oscillator. To provide stability, the typical value of the input capacitance of the crystal oscillator can be selected to be 20 to 30 pF.

2.2.2 Frequency selection

According to the sampling theorem, the greater the ratio of the clock frequency fref (fref/2 is the Na-quist frequency) to the quantization noise power, the redundant signal level, and the interference signal in the output spectrum due to failure to meet the sampling theorem, the clock frequency and the reference reference frequency fo_DSS of the phase detector (i.e., the signal frequency fref/fo_DSS obtained from DSS), the less interference the output signal spectrum of the frequency synthesizer will receive. The specific calculation method of the clock frequency is as follows:

Assume that the output frequency of the frequency synthesizer composed of the DDS-based PLL is 906.24 MHz (to be distinguished from the output signal frequency fo_DSS obtained by DSS, i.e. the reference frequency of the phase detector), after 256 or 512 division (optional), assuming 256, then the output signal frequency fo_DSS of the DDS should be equal to 906.24/256=3.54 MHz, and the calculation formula of the output frequency of the PLL can be obtained:

Where: the pre-mark value N can be selected as 256 or 512, and DDS_x is the value of the control word A or B.

The DSS frequency value can be programmed through the serial port control word, the least significant bit is 2°, and the most significant bit is 223. The two highest bits (bits 23 and 22) are not accessible to users, and are automatically set to 0, 21-0, and are programmed by the user. Among them, the A word corresponds to the frequency of DDS-O, that is, mode 0; the B word corresponds to the frequency of DDS-1, that is, mode 1; the C word controls the settings of the PLL, data limiter, and mode 1 register; the D word controls the modulation mode (such as the frequency deviation) and the settings of the mode O register.

2.3 Carrier frequency calculation

The carrier frequency of the VCO output can be obtained by passing the clock frequency through the DDS-based frequency synthesizer. For a typical clock frequency of 25.6 MHz, it can be obtained from Table 1 that when the DDS control word is 001, 000, 111, 0000, 000, 000, the calculated VCO output frequency, i.e. the carrier frequency, is 915 MHz.

From Table 1, we can see that:

The final VCO output frequency is:

2.4 Calculation of DSS control word

The FSK modulation of TRF6900 is completed by a special FSK frequency deviation register. The A and B control words are used to set the frequency and channel of the receiver and transmitter. In the application system, the A and B control words are used to set the FSK frequency deviation. The calculation method of the DDS control word for FSK mode is as follows:

Assume that the carrier frequency is 915.0 MHz and the frequency deviation is 20 kHz, that is, the VCO output frequency fout1 corresponding to the A word is 915.00 MHz; the VCO output frequency fout2 corresponding to the B word is 915.02 MHz; the clock frequency fclock=fref=25.6 MHz; the frequency division ratio N=256. The A and B control words are calculated as follows:

The A word corresponds to the DDS_O value:

The resulting binary DDS_O will be loaded into the A control word.

The B word corresponds to the DDS_1 value:

The resulting binary DDS_1 will be loaded into the B control word.

2.5 Local Oscillator

The local oscillator (LO) of the TRF6900 is a phase-locked loop (PLL) consisting of an on-chip DDS-based frequency synthesizer, a low-pass filter (LPF) and a voltage-controlled oscillator (VCO).

2.5.1 VCO Circuit Design

A voltage controlled oscillator is an oscillator whose output signal frequency varies with the input control voltage. In order to reduce phase noise, the VCO circuit is usually constructed with discrete components.

The resonant frequency of the LC resonant tank circuit is:

Inductance value at resonant frequency:

Where: |ZIN| is the input impedance of the internal oscillator of TRF6900; QLOAD is the quality factor of the resonant circuit; QP is the quality factor of the inductor; f is the resonant frequency.

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2.5.2 VCO Sensitivity

The capacitance of the varactor diode is proportional to the tuning voltage, and the sensitivity of the VCO is:

2.5.3 Parameter calculation

The designed wireless transceiver circuit works in the 868-928 MHz ISM band. Assume that the VCO output frequency of TRF6900 is 880-950 MHz and the tuning voltage is 0.3-2 V. The input impedance of TRF6900 oscillator |ZIN|, i.e. the resistance between pins 13 and 14, is about 1 400 Ω; the quality factor of the resonant circuit must be greater than or equal to 10; at 915 MHz, the quality factor of the inductor is about 80. From the formula, we can get: L≤10.65 nH, and take L=10 nH as the standard value.

From the equation we know that:

In order to expand the tuning range of the varactor diode, according to the above calculation, C2 can be taken as 2.2pF and C1 can be taken as 3.3pF.

The design uses the SMV1247 series varactor diode from Alpha Industries, with the following parameters:

It should be noted that because the distributed capacitance of the PCB is unpredictable and changes with the operating frequency, necessary corrections must be made during PCB debugging. Here, empirical values ​​are used.

Now verify the above component parameters:

For ftune at 0.25 V, according to the formula, CTOTAL = 3.346 pF;

For ftune at 2.00 V, CT0TAL = 2.799 pF.

From the above equation, we can know that the resonant frequency of the tank circuit is: MHz,,2 MHz. Obviously, it can meet the frequency tuning range of 880～940 MHz. For the component parameters that meet the frequency tuning range of 880～940 MHz, take L=10 nH, C1=3.3 pF, C2=2.2 pF, and the varactor diode is SMVl247-079. Finally, the sensitivity of VCO can be obtained as MHz/V.

2.5.4 Loop Filter Design

(1) Calculation formula

The loop filter is a typical second-order low-pass filter used in the charge pump current mode of the frequency synthesizer. The calculation formula of the second-order components is:

Where: KPD is the phase detector gain (unit: A/rad), KPD=ICP/2π; KVCO is the VCO gain (unit: rad/V); N is the frequency division ratio; ζ is the damping ratio, the effective range is 0<ζ<1, and the typical value is 0.707; ωN is the natural resonant frequency (unit: rad/sec), ωN=(2×BN)/[(ζ+1)/2]2.

(2) Design considerations

The VCO has two operating modes: accelerated and normal, and the latch time is less than 250μs. The normal mode is used to accurately control and maintain the required frequency of the VCO; the accelerated mode uses the APLL phase-locked loop acceleration factor to provide fast coarse adjustment, which can be adjusted as needed using the TRF6900 software. The resonance of DSS is usually within the loop bandwidth and cannot be suppressed by the loop filter, but reducing the bandwidth of the loop filter can reduce the possibility of DSS harmonics. Correctly selecting the clock reference frequency can better suppress DSS harmonics.

3 System Software Design

The software part mainly consists of the main program and various subroutines. The main flow chart includes two parts: one is the device initialization; the other is the loop part (loop main) to set the relevant loop program. The initialization part mainly sets the port, mode and clock system; the loop part (loop main) provides RS 232 and radio frequency (RF) communication, including the initialization of the checksum. Due to space limitations, it will not be introduced here.

4 Conclusion

This design is based on the characteristics of the TRF6900 transceiver chip and the advantages of the microcontroller MSP430F112. The wireless data transceiver system has been designed. After many experiments, it has been proved that the transmitter can correctly transmit the data; at the same time, after the TRF6900 transmission, the receiver can also correctly receive and display the data. The system has completed a relatively complete hardware design and anti-interference measures. In the future, the system software will continue to be developed, so that the safety and reliability of the system can be guaranteed, and it has universality, which is easy to put into practical application and has a wide range of market application value.