Design Technology of Multiple Serial Ports in Single Chip Microcomputer System

1. Introduction

In the measurement and control system with single-chip microcomputer as the core, the microcontroller often needs two or more serial ports to communicate with other hosts or peripherals. How to make the system have multiple serial interfaces is a universal problem. Especially in the field of aerospace, since GPS, atmospheric data system, digital compass, radio altimeter, and even gyroscope and other avionics equipment generally use serial communication, the single-chip computer system needs multiple serial ports to meet the needs of information exchange with the outside world.

2 Commonly used multi-serial port design methods

① Choose a single-chip microcomputer with multiple serial ports

Directly choosing a multi-serial port microcontroller as the system's CPU is obviously the most direct and effective method. Now many new CPUs are equipped with two or more serial ports, such as W77E58, DS80C320, MSP430F149, C8051F020 microcontrollers and digital signal processor TMS320C30 have two serial ports, while Cygnal's C8051F series microcontrollers have 4-5 full-duplex asynchronous serial ports.

②Use CPU I/O to simulate serial port

When the baud rate of the serial port is set to 9600 baud, it takes about 100 us to transmit a bit. For general single-chip microcomputers, the software timer is fully capable of simulating the timing of the serial port according to the asynchronous serial communication protocol. Therefore, using two I/O ports of the CPU and a software timer, a serial port can be simulated purely by software. The literature introduces a specific implementation method. When sending, it only needs to output data one bit at a time. When receiving, first use the external interrupt to detect the starting level on the I/O receiving port, then use the timer to delay the reception of the first bit of data by half a bit, and then delay the reading of other bits of signals by one bit.

③ Software serial port based on high-speed input and output

The 80C196 series microcontrollers are equipped with high-speed input HSI and high-speed output HSO interfaces. HSI and HSO can be used to simulate serial ports. HSO is used to output data. As long as the delay time corresponding to the baud rate is written in the HSO timer, HSO will output a data bit each time it is interrupted until the stop bit is output. When receiving, the start bit is detected using the signal jump detection function of HSI itself, and an interrupt is generated to notify the CPU to start receiving data. The subsequent data bits are read by the software timer according to the baud rate. The literature introduces the implementation method in detail and gives the complete program code; this method is used in the 80C196 MC/MD microcontroller. It is manifested as the application of the event processing array EPA and the peripheral transaction server PTS. Its advantage is that each module of the EPA corresponds to the specified pin of the CPU, reducing software overhead and the complexity of program design.

④16C550 series programmable communication controller

There are many types of interface chips that use parallel ports to expand serial ports. Among them, the 16C550 series communication controllers are widely used in computer control systems and communication equipment to realize the communication between the CPU and the serial port and MODEM. The 16C550 is equipped with one serial port, the 16C552 is equipped with two serial ports, and the 16C554 is equipped with four serial ports. The essence of the 16C550 series devices is to realize the conversion between the serial port and the CPU parallel port, and it has strong digital logic functions. The serial port working mode of the 16C550 series devices is programmable, and some also have a switch input and output interface, which can be used as the switch expansion interface of the CPU.

⑤Use discrete devices to convert parallel ports into serial ports

The document provides a circuit that uses discrete components such as a 555 timer, a D flip-flop, and a shift register to achieve serial and parallel port conversion. The circuit uses a timer to generate a synchronous clock signal that is consistent with the baud rate, shifts the received data to the parallel port for the CPU to read, or shifts the data from the parallel port to send it out. In essence, it uses several discrete components to simulate the functions of 16C550.

⑥Serial port expansion chip

There is a special SP series serial port expansion chip that can expand a high-speed full-duplex serial port into multiple low-speed full-duplex serial ports. The baud rate of the serial port is uniformly determined by the crystal oscillator. For example, SP2328 and SP2338 can expand a mother serial port into three sub-serial ports, and SP2538 can expand a mother serial port into five sub-serial ports. This series of chips has input address lines and output address lines. When sending data from the mother serial port to the sub-serial port, the output address line should be selected to determine which sub-serial port is output. When reading data from the sub-serial port through the mother serial port, the level of the input address line should be detected to determine which sub-serial port signal is. This series of chips should adopt a time-sharing mechanism to decompose one data into multiple channels or combine multiple data into one channel through the internal logic circuit. For example, the baud rate of the SP2328 mother serial port is four times the baud rate of the sub-serial port, and the baud rate of the SP2538 mother serial port is six times the baud rate of the sub-serial port.

⑦Use multiplexer to expand serial port

The document provides a method of using the multiplexer MAX353 to expand one serial port into two. When sending a signal, the CPU first gives the port selection address of the MAX353, and the serial signal is sent out from the specified channel after switching the multiplexer. When receiving a signal, the multiplexer is set to the first channel by default, and the RXD2 of the second serial port is simultaneously connected to the external interrupt pin of the 2PU. If there is data in the first channel, it is directly received. If there is data in the second channel, the start bit of RXD2 will generate an external interrupt, and the CPU enters the interrupt response program, switches the multiplexer to the second channel, and receives the data of RXD2. After a byte is received, the multiplexer is switched back to the first channel.

The method in the literature occupies an external interrupt and can only expand one serial port into two. Based on the same idea, a four-to-one multiplexer can be used to expand one serial port into more than two.

The data operation process is the same as above. In order to realize data reception, a channel selection circuit needs to be designed using a programmable logic device or latch and encoder. The multiplexer is selected to the channel with the start bit first. The CPU determines the channel number of the received data based on the output of the channel selection circuit. [page]

⑧Use FPGA/CPLD to design serial port

FPGA/CPLD has powerful circuit simulation function. FPGA/CPLD can be used to design the timing logic circuit of parallel port to serial port. The circuit generally consists of four parts: bus interface and control logic part, baud rate generation part, shift output and latch part, shift input and latch part. The baud rate of the circuit can be adjusted, and there are chip select lines and read and write lines. The CPU accesses the circuit through the parallel port. In essence, the circuit simulates the serial interface function of the programmable controller 16C550. In fact, FPGA/CPLD has great flexibility. The circuit can be appropriately tailored according to actual needs and system resources, and multiplexing technology or time division multiplexing technology can be applied to the simulation of the serial port.

3 Comparative Study and Selection Principles of Multi-Serial Port Design Methods

The above eight methods have their own advantages and disadvantages. Obviously, choosing a multi-serial port CPU is the most direct and effective method, but choosing a new model of CPU has certain development risks for developers, and sometimes it is restricted by supply channels and development conditions. Choosing a dedicated chip is a serial port external expansion method with the highest reliability, which has many advantages such as mature technology and small software workload. The disadvantages are increased hardware cost and volume, and sometimes it takes up external interrupt sources. Choose a multiplexer. Its advantages are that it can realize CPU point-to-multipoint communication, low software and hardware costs, and high reliability. The fatal disadvantage is that the CPU cannot receive multiple input data at the same time. Choosing FPGA/CPLD can not only design the serial interface itself, but also be used to realize multi-channel serial port switching, or manage the interrupt sources of multiple serial interface chips. The advantages are high reliability and low CPU software overhead, and the disadvantages are slightly higher development costs and high hardware costs. Using discrete components to realize serial port conversion has the advantages of small software workload, and the disadvantages are complex circuits, poor reliability, and the need to occupy external interrupt sources. The advantages of using software to simulate the serial interface are self-evident. It does not add any hardware and does not occupy external interrupt sources. The disadvantages are high software complexity, high CPU overhead, and the use of software timers.

The above eight multi-serial port design methods can be summarized into five design ideas:

① Start directly from the CPU and choose a single-chip microcomputer with multiple serial ports;

②Exploit the resources of the device itself and use software to simulate the serial port on the CPU I/O port line;

③Use functional circuits to achieve serial and parallel conversion;

④ Use functional circuits to decompose a high-speed serial port into multiple low-speed serial ports;

⑤Realize switching from one channel to multiple channels through time-division multiplexing.

How to choose these different design ideas and their specific implementation methods when applying them should not only be based on the software and hardware complexity, CPU time overhead, real-time and reliability of the above methods, but also on the total number of serial interfaces required in the application system, the independence and baud rate between each serial port, as well as the existing development conditions and comprehensive cost indicators. When choosing, we should make a comprehensive trade-off based on various factors. On the basis of being able to achieve the required functions, we should make full use of existing resources, reduce system complexity, improve reliability, and strive to minimize the design cost and the overall cost. Of course, the selection of these methods should be flexible and diverse. You don't have to stick to one method. You can also choose a combination of several methods according to local conditions.

4 Application Examples

In the design of a certain type of UAV flight controller, the CPU is 80C196KC. The original serial port on the CPU is used for remote control and telemetry. In order to measure the heading angle of the aircraft, the digital compass HMR3000 is used in the system. The sensor is a serial port interface with a baud rate of 19200 and output data in NMEAC183 format, 20 frames per second, and 35 bytes per frame. Therefore, it is necessary to add a full-duplex asynchronous serial interface to the controller.

Based on the comparison and analysis of the above eight design methods, after weighing the complexity of the system's hardware and software, the fourth method was selected, that is, using the 16C550 programmable communication controller to expand a serial port. It is specifically used to communicate with the sensor. The 16C550 uses the FIFO function and makes an interrupt request to the CPU after receiving 14 bytes. In this way, the CPU can receive all one frame of attitude measurement data with a maximum of four interrupts. The controller software only takes 1.187ms to decode one frame of HMR3000 output data, and the burden on the CPU is not large. The connection circuit of the CPU, 16C550 and HMR3000 is shown in Figure 1.

Figure 1 Interface circuit diagram between programmable communication controller 16C550 and single-chip microcomputer system