Low Power Design in Embedded Systems

After rapid development in recent years, embedded systems have become the most promising branch in the electronic information industry. With the widespread application of emerging products such as mobile phones, PDAs, GPS, and set-top boxes, the market for embedded systems is increasing at an annual rate of 30% (IDC forecast), and the design of embedded systems has become a topic of increasing concern to software and hardware engineers.

In the design of embedded systems, low-power design is a problem that many designers must face. The reason is that embedded systems are widely used in portable and highly mobile products, and these products do not always have sufficient power supply, and are often powered by batteries. Therefore, designers consider reducing power consumption from every detail to extend the battery life as much as possible. In fact, considering low-power design from a global perspective has become an increasingly urgent issue.

So, from which aspects should we consider low power design? I think we should consider the following aspects comprehensively:

1. Processor selection

2. Interface driver circuit design

3. Dynamic Power Management

4. Selection of power supply circuit

Let's discuss each of them separately:

1. Processor selection

When we select an embedded system, we usually start with its CPU and operating system (OS). Once these two are selected, the entire system framework is selected. When we choose a CPU, we usually pay more attention to its performance (such as clock frequency, etc.) and the number of interfaces and functions it provides, and often ignore its power consumption characteristics. However, because the CPU is the main source of power consumption in embedded systems---for handheld devices, it almost accounts for the entire system power consumption except for the display screen.

The CPU accounts for more than half of the power consumption (depending on the specific situation of the system), so choosing the right CPU has a significant impact on the final system power consumption.

Generally, we compare and select CPUs based on their performance and power consumption. Usually, we can use the energy consumed per execution of 1M instructions to measure it, that is, Watt/MIPS. However, this is only a reference indicator. In fact, the architectures of various CPUs vary greatly, and the methods of measuring performance are also different. Therefore, we should further analyze some details.

We divide the power consumption of the CPU into two parts: the core power consumption PCORE and the external interface controller power consumption PI/O. The total power is equal to the sum of the two, that is, P=PCORE+PI/O. For PCORE, the key lies in its power supply voltage and clock frequency; for PI/O, in addition to paying attention to the power consumption of each dedicated I/O controller, you must also pay attention to the address and data bus width. The following discusses the two separately:

1. CPU supply voltage and clock frequency

We know that in digital integrated circuit design, the static power consumption of CMOS circuits is very low, which is basically negligible compared with its dynamic power consumption, so we will not consider it for now. The dynamic power consumption calculation formula is:

Pd=CTV2f

Where, Pd---dynamic power consumption of CMOS chip

CT----Load capacitance of CMOS chip

V----The operating voltage of CMOS chip

f-----The operating frequency of the CMOS chip

From the above formula, we can know that the power consumption in CMOS circuit is linearly related to the switching frequency of the circuit and quadratically related to the power supply voltage. For a CPU, the higher the Vcore voltage and the faster the clock frequency, the greater the power consumption. Therefore, under the premise of being able to meet normal functions, choosing a CPU that works at a low voltage as much as possible can achieve better results in terms of overall power consumption. For the CPU that has been selected, reducing the power supply voltage and operating frequency is also a feasible way to save power. [page]

2. Bus width

We often fall into a misunderstanding that the wider the CPU external bus width, the better. If we only talk about data transmission speed, this view may be correct, but if it is a design that is very sensitive to power consumption, this view may not be correct.

Similarly, the formula Pd=CTV2f is used. For each line (address and other data lines), there will be such power consumption. Obviously, when the bus width is wider, the power consumption will naturally be greater. The capacitive load of each line is different, but it is generally between 4 and 12PF. Let's look at the following example: a 1Mbit Flash is connected through 8bit and 16bit

The bus is connected to the CPU, the bus frequency is 4MHZ, and the bus voltage is 3.3V. We can get the following results:

As can be seen from the above, there is a 3.7mW power consumption difference between using a 16-bit bus and using an 8-bit bus.

Of course, if a large amount of data needs to be accessed frequently, using an 8-bit bus may not be economical because it increases the read and write cycles.

In addition, from the above example we can also see that if the CPU uses built-in Flash, the system power consumption can be greatly reduced.

2. Low power consumption design of interface driver circuit

The low power design of the interface circuit is often a link that is easily overlooked. In this link, in addition to considering the selection of peripheral chips with low static current, we should also consider the following factors:

1. Selection of pull-up resistor/pull-down resistor

2. Treatment of dangling feet

3. The necessity of Buffer

Usually we are used to arbitrarily determine a pull-up resistor value without careful calculation. Now let's do a simple calculation. If a 4.7KΩ pull-up resistor is used in a 3.3V system, when the output is low, the current consumption on each pin is 0.7mA. If there are 10 such signal pins, there will be 7mA current consumption on them. So we should consider choosing a larger resistance value as much as possible while being able to drive the subsequent stage normally (that is, considering the VIH or VIL of the IC). The pull-up resistor value in many application designs is even as high as several hundred KΩ. In addition, when a signal is low in most cases, we can also consider using a pull-down resistor to save power.

We should also pay attention to the floating pins of CMOS devices. Because the input impedance of the floating input of CMOS is extremely high, it is likely to induce some charge and cause the device to be broken down by high voltage. It will also cause the input signal level to change randomly, causing the CPU to be constantly awakened when in sleep mode, thus failing to enter sleep mode or other inexplicable failures. Therefore, the correct way is to connect the unused input to VCC or ground.

Buffer has many functions, such as level conversion, increasing driving capability, data transmission direction control, etc., but if we only consider the driving capability, we should consider carefully, because overdriving will lead to more energy being wasted. So we should carefully check whether the maximum output current IOH and IOL of the chip are sufficient to drive the lower IC. If we can avoid the use of buffer by selecting the appropriate front and back chips, it will be a great energy saving.

3. Dynamic Power Management (DPM)

The so-called dynamic power management is to save power by dynamically controlling the system clock or voltage during system operation. This dynamic control is closely related to the operating status of the system, and this work is often implemented through software.

1. Select different working modes

As mentioned above, the system clock has a very significant impact on power consumption. Therefore, in addition to focusing on meeting performance requirements, we must also consider how to dynamically set the clock to achieve maximum power savings. The various frequencies inside the CPU are generated by multiplying the external crystal frequency through the internal phase-locked loop (PLL). Therefore, whether the various operating frequencies can be set through internal registers becomes a key factor in controlling power consumption. Now many CPUs have multiple working modes, and we can achieve power saving by controlling the CPU to enter different modes.

Let's take SAMSUNG S3C2410X (32bit ARM 920T core) as an example. It provides four working modes: normal mode, idle mode, sleep mode, and shutdown mode. The power consumption of each mode is as follows:

As can be seen from the above figure, the CPU consumes much more power when running at full speed than when it is idle or in sleep mode. The principle of power saving is to make the normal operation mode take up much less time than the idle and sleep modes. In devices like PDAs, the system runs at full speed much less than when it is idle, so we can set the CPU to work in idle state as much as possible, then wake up the CPU through the corresponding interrupt, restore to normal working mode, process the response event, and then enter idle mode.

2. Turn off unnecessary peripheral controllers

Generally speaking, CPUs provide a variety of interface controllers, such as I2C, I2S, LCD, Flash, Timer, UART, SPI, USB, etc., but these controllers are generally not all used in a design, so we often leave these unused controllers in various states without paying attention to them. However, if you want to save power as much as possible, you must pay attention to their status, because if you do not turn them off, even if they are not in working state, they will still consume current. Still taking S3C2410X as an example:

From the table above, we can see that by setting registers, we can selectively turn off unnecessary functional modules to save power. For example, in our actual application, ADC, I2C, I2S and SPI are not used. By setting the CLKCON register, we can save 2mA of current. Of course, we can also dynamically turn off some peripheral controllers that are still needed to further save energy. For example, in idle mode, the CPU core stops running. We can also further turn off some other peripheral controllers, such as USB, SDI, FLASH, etc., as long as the I/O controller that wakes up the CPU works normally. For example, if it is woken up by UART, the UART controller cannot be turned off. After the CPU is awakened, turn on the USB, SDI, Flash and other controllers again. [page]

The above two methods are only the simplest implementation of dynamic power management. In these two methods, one is to change the system clock frequency, and the other is to control the switch of the peripheral controller to achieve the purpose of energy saving. In recent research, some people have turned their attention to dynamically changing the voltage and frequency of the processor at the same time to further save power, such as the research on dynamic power management of embedded systems conducted by IBM and MontaVista. This is a more complex and systematic project, which involves relevant content from hardware to operating system and application layer.

4. Power supply circuit

In digital circuit design, engineers are often accustomed to using the simplest way to complete the power supply design, but when there are strict requirements on power consumption, we must carefully consider what voltage conversion structure to use before making a decision.

Generally speaking, we have the following ways to convert voltage:

1. Linear Regulator

2. DC to DC

3. LDO（Low Drop-Out）

Among them, LDO is essentially a linear voltage regulator, which is mainly used in occasions with small voltage difference. Therefore, we combine it into linear voltage regulator for discussion.

For linear voltage regulation, its characteristics are simple circuit structure, small number of components required, and large input and output voltage difference, but its fatal weakness is low efficiency and high power consumption. Its efficiency η depends entirely on the output voltage. The figure below is a curve of the output current size relative to the voltage difference of the linear voltage regulator LM7805.

As can be seen from the figure, the larger the voltage difference, the smaller the maximum output current that can be provided. Assuming that LM7805 is used, the input is 12V, the output voltage is 5V, the voltage difference is 7V, and the output current is 1A, we can calculate that the power consumed by the linear regulator is P=ΔV*IOUT=7*1=7w, and the efficiency is only η＝5×1/(5*1+7*1)= 41.7%. From this result, we can see that more than half of the power is consumed by the IC itself.

The characteristics of DC to DC circuit are high efficiency and flexible step-up and step-down, but the disadvantage is that the circuit is relatively complex and has large interference. Generally, there are two common circuits: Boost and Buck. The former is used for step-up and the latter is used for step-down. The schematic diagram is as follows:

The core of these two circuits is to control the energy conversion between inductance and capacitance through the switch of MOS tube. Adjusting the duty cycle of the MOS tube gate pulse signal can control the conduction and shutdown of the MOS tube, thereby changing the output voltage.

The figure below is a DC to DC circuit diagram for converting from 12V to 5V. Its control IC uses the LM2596 of National Semiconductor (NS). It actually uses a Buck circuit. Its MOSFET and related control circuits are located inside the chip. Its conversion efficiency diagram is as follows:

From the conversion efficiency graph, it can be seen that when the input is 12V and the output is 5V, the conversion efficiency is about 82%, which is twice the conversion efficiency of the linear regulator. The switching frequency of LM2596 is fixed at 130KHZ. If we increase the switching frequency of the device, such as using NS's LM2676 (260KHZ switching frequency), under the same application conditions, the efficiency can reach more than 88%.

From the above discussion we can see that using DC-DC voltage conversion circuits under appropriate circumstances can effectively save energy and reduce the power consumption of the entire machine.

References:

1、 Dynamic Power Management for Embedded System, Version 1.1 November

19, 2002, IBM& MontaVista Software

2、 Low Power Design , Dec 28 2001, Mike Willey & Kris Stafford, www.

embedded.com

3、 System Level Power-Performance Trade-Offs in Embedded Systems Using

Voltage and Frequency Scaling of Off-Chip Buses and Memory, Kiran

Puttaswamy, Kyu-Won Choi, Jun Cheol Park et al