Several ISP programming methods for P89LPC932

Introduction:

LPC900 series Flash microcontrollers provide packages ranging from 8-pin to 28-pin, which can meet the needs of various applications that have limited cost and circuit board space but require high performance and high reliability. At the same time, they have the characteristics of high speed (6 times that of traditional MCS51 microcontrollers), low power consumption (less than 1 μA in full power-down mode), high stability, small package, and multi-function (embedded with many popular functional modules). P89LPC932 is an important member of this family, which integrates 8 KB Flash program memory, 512B static data memory, 512B E2PROM, I2C bus, SPI bus, enhanced UART interface, analog comparator, watchdog, 4 interrupt priority levels, dual DPTR, and supports ISP/IAP programming and other functions.

1 Basic way of ISP programming of P89LPC932

1.1 Three programming methods of internal program memory

The three programming methods of the 8 KB program memory integrated in P89LPC932 are: in-system programming (ISP); program runtime programming (IAP); programming through parallel mode.

Generally speaking, ISP programming refers to relying on some external tools (except conventional parallel programmers) to directly program the program memory integrated in the processor. There are many common external tools referred to here, and different processor suppliers may provide different solutions. For example, according to different programming interfaces, there are JTAG, single-wire, serial port, SPI port and other methods. Although the programming methods are different, the principles are similar, that is, relying on external conditions to trigger the processor, so that it deviates from the normal execution of the internal regular user application code process, and instead executes the code that controls the erasure of program memory and programming of program memory stored in a fixed position in its program storage space (or the execution code provided by the processor outside), and then through some communication method with the PC computer, a user-specified binary code file that can be run by the embedded processor compiled on the PC is programmed into the program memory in the embedded processor. This programming method only requires conventional hardware configuration (some processors may require some simple hardware circuits called download lines) support, but does not require special programmers (parallel programmers) support, so programming can be achieved even if the processor chip has been soldered to the circuit board. This is the true meaning of ISP. P89LPC932 uses its own asynchronous serial port to implement ISP programming, and does not require special download lines or downloaders. The method of triggering LPC932 to enter ISP programming mode will be explained in detail below.

IAP programming is similar to ISP programming, but it is not triggered by external conditions. Instead, when the processor executes the user-designed application code normally, it directly calls the solidified routines that execute the erase and programming functions. Like ISP programming, IAP programming only requires conventional hardware configuration support. P89LPC932's ISP programming is actually implemented by calling the chip's IAP service subroutine. Its IAP service subroutine is stored in the FF00H~FFFFH address space and does not occupy the user program space. Parallel programming

requires the use of an external professional programming device. In other words, this programming environment is not the hardware environment for the user's final application. When using this programming method, users usually have to put the processor chip separately on the parallel programmer for programming (if the processor chip has been soldered to the circuit board, the processor chip must be removed from the circuit board first). The processor chip can only be put back on the circuit board after programming is completed, and then the processor can be powered on to run, and the running results of the user's newly written code can be seen. This is the most traditional programming method (the classic AT89C51 is mainly programmed in this way), but it is cumbersome and cannot meet the actual needs of today's remote upgrades. Therefore, it has gradually been replaced by convenient and fast online programming methods such as ISP and IAP.

In general, the ISP mode is the easiest to use because it allows the processor to be programmed after being soldered to the user's target circuit board, and does not require complex code design. This feature allows users to upgrade product software after the hardware product is produced. Generally speaking, adding calibration information data and installing the latest software version on site are more common upgrade operations. Not only that, ISP programming is also particularly suitable for the user's product development stage. Obviously, users can change their program code very conveniently and quickly and immediately see the running results of the new code. P89LPC932 uses the serial port as the main communication interface of the ISP programming mode, making this series of processors more convenient than those processors that rely on communication interfaces such as JTAG and SPI as ISP programming interfaces. Because general embedded systems are equipped with asynchronous serial ports, in this way, no special ISP programmer is required for in-system programming, while JTAG, SPI and similar programming methods generally require dedicated interface adapters or download cables to cooperate, which may increase the user's investment and cost. The

ISP programming of the P89LPC932 chip relies on a startup code preset at the factory. This code is stored at the high-end 512B address of sector 7 in the P89LPC932 code space (the 8 KB program memory inside the P89LPC932 is organized into 8 sectors, each with 1 KB). This code provides an interface between the device's underlying operation code (performing operations such as erasing and programming) and serial communication. If the user needs to use the ISP programming mode, it must be noted that the sector containing the ISP preset code, that is, sector 7 (1C00~1FFFH), must not be erased or overwritten, because the erase operation of P89LPC932 is based on sectors as the basic unit.

As shown in Figure 1, the hardware connection of using P89LPC932 to implement ISP is very simple. It only needs to use VDD voltage to execute the erase and programming algorithm, and does not require a special high programming voltage. Therefore, only one chip for TTL and RS232 level conversion is needed outside the chip (common chips include Maxim's MAX202, MAX232, etc., and other companies such as TI, Sipex, Linear have chip products with similar functions) to realize the connection between the asynchronous serial port in P89LPC932 and the RS232 serial port on the user's personal computer. ISP programming can be achieved by running a simple terminal emulation program on the user's personal computer, but there is an even simpler way to achieve this goal, which is to run a ready-made free program, such as Flashmagic, which integrates all ISP functions for the Philips LPC900 series processors. The ISP code inside the P89LPC932 can automatically detect the baud rate of its on-chip asynchronous serial port communicating with the user's personal computer, thereby realizing code download and programming under the control of the user's personal computer. In summary, this ISP programming mode of the P89LPC932 does not require an external programmer, but requires certain external circuits (serial port communication circuits), requires the retention of ISP resident code, requires the addition of ISP boot initialization procedures (such as abort control character detection initialization) in the user's application code, and the second bit of the ISP encryption word (prohibiting ISP/IAP erase) cannot be set.

Figure 1 P89LPC932 ISP mode hardware connection diagram

1.2 Methods to enter ISP mode

There are four methods to trigger P89LPC932 to enter ISP mode: enter ISP mode by detecting the status bit (the default state when a new chip is initially powered on); enter ISP mode by detecting the abort control signal and triggering reset (the most practical and commonly used method); trigger enter ISP mode after detecting a specific pulse on the reset pin during power-on (i.e. hardware activation to enter ISP mode); directly call the ISP code to enter ISP mode.

1.2.1 Enter ISP mode by detecting the status bit

When the P89LPC932 is reset, whether to enter the ISP mode is controlled by a status bit. This status bit is saved in a reserved position in the Flash memory, but this position is not in the program memory space that the P89LPC932 can address. At the falling edge of the reset signal, the processor will check the value of the status bit. If its value is 0, the processor will start fetching instructions from address 0000H, where the user's application code is usually stored. If the value of the status bit is not 0, the processor will start executing the code here from another determined address. The high 8 bits of this address (16 bits) are specified by the reset vector, and the low 8 bits are fixed to 00H. In other words, the value of the boot vector will be used as the high byte of the program counter (PC), and the low byte is 00H. If the user is using a new chip, the status bit value in the chip is set to 1 at the factory, and the startup vector is pre-programmed to 1EH. Therefore, the new chip will directly start executing the code from the address 1E00H after reset. Because the code starting from 1E00H is exactly the ISP startup code preset by Philips for the chip. If the user wants to start executing the code from address 0000H, the value of the status bit can be cleared by a parallel programmer. In fact, the status bit can also be cleared by the ISP code itself; if the user writes his own application code to the program memory inside the P89LPC932 and clears the status bit, the processor will directly execute the user code after the next chip reset. In addition, the ISP code also has the function of modifying the startup vector value. The user can modify its value, that is, modify the address where the code is executed after the chip is reset (if the LPC932 is triggered to enter the ISP mode), and the startup code written by the user is placed there. This design is usually used to perform certain special functions. However, if the user modifies the startup vector value so that it is no longer 1EH, the user can no longer use the startup code preset by the LPC932 when it leaves the factory. If the startup vector is modified to point to an address that does not include any startup code, the user has to use a parallel programmer to program the chip to restore its startup vector value; otherwise, the user will no longer be able to use this ISP programming method. [page]

1.2.2 Entering ISP mode by detecting the abort control signal to trigger the chip reset

Entering ISP mode by detecting the abort control signal through the asynchronous serial port to trigger the chip reset is the second way to enter ISP mode. The abort control signal refers to the low level of the receiving pin of the asynchronous serial port for a frame length. The length of a frame here is related to the working mode of the asynchronous serial port. For example, in the "mode one" of the asynchronous serial port, a frame is equivalent to the transmission time of 10 bits. Generally, when a break control signal is issued, the receiving pin of the asynchronous serial port will continue to be low for many frame times. However, the break control signal will be detected in the first frame. Note that if a mechanical switch is used to pull down the receiving pin of the asynchronous serial port to create a break control signal, and the processor is configured to allow serial interrupts, the receiving interrupt flag of the asynchronous serial port must be processed during the entire interrupt service process, otherwise the processor will enter an uncertain state.

This method requires that the user application code residing in the P89LPC932 program memory must include the code to initialize the asynchronous serial port. In other words, the user must enable the asynchronous serial port, and the break control character signal bit (EBRR) in the special function register AUXR1 must be set to 1 to allow the processor to reset when the break control character signal is detected. In addition, the startup vector configuration byte must be guaranteed to be 1EH (using the ISP code preset in P89LPC932), the status word is 00H (to enable the user application code to execute), and the Flash program memory from 1E00H to 1FFFH should not be used or erased. After the configuration is completed, as long as the asynchronous serial port receiving pin detects the break control character signal, the processor will reset, and after the reset, the LPC932 will fetch instructions from the address specified by the startup vector.
There are two problems that should be understood when using this trigger method. First, some USB to RS232 converters cannot send a break control character signal, so it is impossible to use the method of detecting the break control character signal to trigger the processor reset and enter the ISP mode; second, the break control character signal will not appear in normal serial port communication, so users can use this trigger method with confidence.

1.2.3 Hardware activation to enter ISP mode

The advantage of using this mode is that no matter what user code is originally stored in the processor, and no matter what the value of the status bit is, the ISP mode can always be entered (but one thing must be guaranteed, that is, the original startup code in the processor has not been erased or overwritten, and the default startup vector 1EH has not been modified). Since the P89LPC932 has a relatively small number of pins, built-in program memory, and no traditional P0, P2 ports and PSEN pins for external expansion buses, the method of triggering the chip to enter ISP mode by hardware is different from that of traditional MCS-51 chips.

After power-on, if the processor detects the pulse waveform shown in Figure 2 on the reset pin, the processor will fetch instructions from the address specified by the startup vector, that is, enter ISP mode, instead of fetching instructions from 0000H. In fact, the result of this entry method has the same effect as having a non-zero status byte. However, it should be noted that the number of pulses generated is only allowed to be 3, and more or less than 3 pulses cannot trigger the processor to enter ISP mode.

Figure 2 P89LPC932 hardware activated ISP mode waveform

An external microprocessor can be used to generate these three pulses, and it also controls a power chip to generate the power supply voltage required by P89LPC932. The principle of this method is easy to understand, and I will not go into details here. In addition, there is a simpler method, which is to directly generate the required timing by adding some hardware circuits to the asynchronous serial port on the user's PC. For details, please refer to Reference 1.

1.2.4 Direct call method

to trigger the processor to execute ISP code The preset start vector of the ISP mode of P89LPC932 is 1EH, so the first address of its ISP resident code is 1E00H. To enter ISP, just call the code at 1E00H directly. In C code, the program can call the ISP resident code (that is, enter ISP mode) through function pointers.

1.3 Using Flashmagic on P89LPC932

Flashmagic is a free software tool that can perform ISP programming for many Philips processors, including P89LPC932. When FlashMagic starts, it will try to connect to the device selected by the user, but usually an error will be reported here because there is no processor in ISP mode, or there are other settings that need to be changed. Please select the correct serial port on the PC controlled by FlashMagic, and select the target device as P89LPC932, as shown in Figure 3. Then put this P89LPC932 into ISP mode (if

Figure 3 FlashMagic startup screen [page]

This is a brand new processor, it is already in ISP mode at this time). If it is not a brand new processor (the status bit is not 1), then you must use hardware to activate the processor to enter ISP mode, or use the detection of the abort control signal to trigger the processor reset and enter ISP mode.

If the processor reset and ISP mode are triggered by detecting the break control signal, as shown in Figure 4, Flashmagic should be configured to use this method to initialize the ISP mode. First, check the "advanced options" option under the "options" menu. On the "hardware config" page of the pop-up dialog box, the "Use DTR and RTS to enter ISP mode" selection box should be unchecked (Note: FlashMagic can remember your various settings. The next time you use it again, if no other settings are needed, you can use it without setting it). Then, select the option "start bootrom" from the "ISP" menu, and select the "send break condition" button from the pop-up dialog box. Flashmagic can directly send a break control signal to the P89LPC932 through the PC serial port. Generally speaking, the P89LPC932 should be in ISP mode at this time. However, Flashmagic will not automatically verify whether the P89LPC932 has actually entered the ISP mode. This work needs to be done by the user. If the P89LPC932 is not in ISP mode, several Flashmagic menus are unavailable
(even if the user selects these menus, Flashmagic will report an error and no execution results will be obtained). The user can check whether the P89LPC932 is already in ISP mode by selecting these menus, such as the "Blank Check..." option under the "ISP" menu. Of course, programming the P89LPC932 is not possible when it is not in ISP mode. In this sense, it can also be known that the P89LPC932 is not in ISP mode.

Figure 4 Interface for sending abort control character conditions

The default setting of Flashmagic is to automatically protect the high-end 512 bytes of boot code in sector 7 of the P89LPC932, but the user can turn off this protection function in the "options-advanced options-security" dialog box. However, it is not recommended for users to do so because it increases the possibility of overwriting the ISP boot code by mistake.

Note that the location of some menu options in the new version of Flashmagic may be different from that mentioned in this article. This article uses Flashmagic version 1.74. As of the time of writing, Flashmagic has been upgraded to version 2.07.

2 Conclusion

Philips P89LPC932 is a high-speed 51-compatible microprocessor with comprehensive functions, simple use, reliable performance and high cost performance. It is suitable for many fields such as product development, small batch product trial production, university scientific research, etc. This article describes in detail the specific methods and techniques of ISP programming of P89LPC932. It is hoped that readers can make full use of the excellent online programming features of P89LPC932.

References
1 Zhou Ligong Microcontroller Co., Ltd. ISP Application Design of P89LPC932, 2004
2 Philips Co. Application Note. In-system programming (ISP) with the Philips P89LPC932 microcontroller, 2003