Configuration of Field Programmable Gate Array Based on Single Chip Microcomputer

1 Introduction

Before the emergence of large-scale programmable logic devices, soldering the device on the circuit board was the last step in designing a digital system. When there were problems in the design and they were solved, the designer often had to redesign the printed circuit board. The design cycle was long and the design efficiency was low. After the emergence of CPLD and FPGA, using their in-system programmable or reconfigurable functions, designers can solder CPLD and FPGA on the circuit board when performing logic design but not circuit design, and then change the hardware logic relationship of the circuit as they please during design and debugging without changing the structure of the circuit board.

2 Structure and Principle of SRAM-Based FPGA

Programmable logic devices can be divided into the following types based on their structure:

⑴ Product term structure device. Its basic structure is an "AND-OR array" device. Most simple PLDs and CPLDs are such devices.
⑵ Lookup table structure device. It is composed of simple lookup tables to form programmable gates, which are then formed into an array. Most FPGA
devices use a lookup table structure based on SRAM. For example, XILINX's XC4000 series, SPATRAN series, ALTERA's
FLEX10K series, and ACEX series are all typical FPGA devices based on SRAM lookup tables. A lookup table (LUT) is a function generator. An N-input lookup table can realize any logical function of N input variables. Currently, 4-input LUTs are mostly used in FPGAs, so each LUT can be regarded as a 16×1bit RAM with 4-bit address lines. When the user describes a logic circuit through a GDF schematic or VHDL language, the FPGA development software will automatically calculate all possible results of the logic circuit and store the results in the lookup table in advance. In this way, when multiple signals perform logical operations, it is equivalent to inputting an address to look up the table, finding the content corresponding to the address, and then outputting it.

3 FPGA Configuration Principle

FPGA uses SRAM cells to store configuration data. These configuration data determine the interconnection relationship and logic function inside the FPGA. Changing these data will also change the logic function of the device. Since SRAM data is volatile, these data must be stored in non-volatile memories such as EPROM, EEPROM or FLASH ROM outside the FPGA device so that the system can download them to the SRAM cells of the FPGA at an appropriate time, thereby realizing in-system reconfigurability ICR (In-Circuit Reconfigurability). ALTERA's FPGA has two configuration download modes: active mode (AS) and passive mode (PS). In the experimental system, debugging is usually performed using a computer or controller, and the passive mode can be used. The programming file generated after compilation and simulation in the FPGA integrated development environment (such as QUARTUSII) is downloaded to the FPGA using a download cable for hardware debugging and verification. After the circuit design is successful, the configuration data is burned and solidified in a dedicated EEPROM (such as EPC1441) produced by ALTERA. When powered on, this piece of configuration EEPROM first loads data to the FPAG, and after tens of milliseconds, the FPGA can work normally.

ALTERA's FPGA has six configuration modes: configuration device, PS (Passive Serial) mode, PPS (Passive
Parallel Synchronous) mode, PPA (Passive Parallel Asynchronous) mode, PSA (Passive Serial Asynchronous) mode, and JTAG (Joint Test Action Group) mode. Among them, the PS mode is the most widely used because the interconnection between the FPGA and the configuration circuit is the simplest and there is no limit on the minimum frequency of the configuration clock. Therefore, the PS configuration method is usually used in the ICR control circuit to implement the ICR function. FPGA devices have three working states: configuration state, initialization state, and normal working state (user mode). Its timing is shown in the figure

4 Configuring FPGA with MCU

At present, many products widely use FPGA. Although the varieties are different, the programming methods are almost the same: use a dedicated EPROM
to configure the FPGA. Dedicated EPROMs are not cheap, and most of them are programmed in a one-time OPT mode. Once the FPGA
design is changed, the cost is not small. Moreover, in the actual application of FPGA, the confidentiality and upgradeability of the design are very important. Using a single-
chip microcomputer to configure the FPGA can solve the above problems well. The timing of the single-chip microcomputer configuring the FPGA in PS mode is the same as Figure 1.
The key to configuration is to use the single-chip microcomputer to generate the appropriate timing.

4.1 Hardware Design

FPGA configuration files are relatively large, usually more than tens of kilobytes. This system configures ALTERA's EPF10K20, whose configuration file size is 29KB. Therefore, an 89C51 microcontroller can be used, and an external 27256 memory can be expanded to store FPGA configuration data. The data transmission between the microcontroller and the FPGA uses a serial port, and the circuit is shown in Figure 2. After the microcontroller is powered on, according to the system requirements, the configuration data stored in the 27256 is downloaded to the FPGA device in the circuit using the P1.1, P1.2, P1.3, RXD, and TXD 5 I/O ports.

Table 1 Configuration pin function description

4.2 Software Design

When programming the software, use the serial port working mode 0: shift register mode. This program is sent in mode 0, the transmit data is output from the RXD pin, and the TXD pin outputs a synchronous shift pulse. When a byte of data is written into the transmit data buffer SBUF, serial transmission is started. Each time a binary number is sent, the register is shifted right by one bit until the eight-bit binary number is sent and the transmit interrupt flag TI is set. The CPU responds to the interrupt and executes the interrupt service routine. Repeat the test CONFIG_DOWN until CONGIG_DOWN is high and the configuration is completed. After that, the FPGA can enter the user working state after initialization.

Figure 3 Main program flow chart

参考文献：
[1] 胡乾斌，李光斌，李玲等。 单片微型计算机原理与应用.武汉：华中科技大学出版社，2002
[2] 潘松，黄继业。EDA技术实用教程.北京：科学出版社，2004
[3] 刘晓明。王军，谢明钦。基于单片机的复杂可编程逻辑器件快速配置方法.电子技术应用