80C196KC-ADMC401 Dual CPU Interface Circuit Design/Application

With the development and widespread application of microcomputer control technology and the increasing complexity and real-time requirements of control systems, many systems need to use two or even more controllers to achieve the various requirements of the controlled objects. Especially in the field of industrial applications, to complete a large amount of data collection and processing, control signal reception and transmission and many other functions, there are very high requirements for the system's computing speed, interface resources, stability and cost. Designing a practical, reasonable and economical high-performance control system is the key to successful field operation.

The SVG (static var generator) device involves a large number of complex calculations (such as filtering calculations, instantaneous reactive power calculations) and advanced control methods (such as vector control) as well as the collection and transmission of many signals, making it difficult for a single CPU to meet system requirements. Therefore, a highly integrated embedded processor and DSP chip are used to form a dual CPU system to achieve control of the entire system.

1. System Design

1.1 System composition and principle

The schematic diagram of the dual CPU system is shown in Figure 1. The system uses two chips, 80C196KC and ADM401, as core processors. ADI's ADM401 chip is a DSP-based controller that is very suitable for high-performance control in industrial applications. The chip integrates a high-speed DSP core, and its core has a complete set of peripheral control interfaces to quickly implement control in a highly integrated environment. Intel's 80C19680C196 (KB/KC) is a high-performance and low-cost 16-bit microcontroller, which is also suitable for high-speed control and occasions requiring multiple peripherals. The two CPUs independently execute programs stored in different devices while maintaining coordination with each other during operation. Considering the complexity of the system itself, if the traditional system wiring method of separating RAM, ROM and logic decoding devices is used, the entire control circuit will inevitably be too complicated, which will bring great difficulties to debugging and reduce the stability of the system. Therefore, the system uses PSD4235 and PSD311 in the PSD product of programmable system peripheral interface device. They are used as external expansion devices of two CPUs respectively, and form a dual CPU-PSD system (referred to as dual CPU system) with the CPU, as shown in Figure 1. The two CPUs use dual-port RAM (IDT7132IDT7132) for mutual communication, through which data transmission between the two CPUs can be smoothly realized. The keyboard management part uses 82C7982C79 interface chip. The output display part uses MGLS-12032A liquid crystal module (LCD) with SED1520SED1520 as the driver chip. An additional serial E2PROM is specially added to the system, which is mainly used for data protection when power is off and recording some operating parameters. In addition, the system also consists of WATCHDOG circuit, UART circuit, etc. The resource allocation and function realization in the system are completed through the software programming of the controller. The following will introduce the interface circuit design of each part and the corresponding working principle in detail. 1.2 80C196KC Partial Design

The 16-bit 80C196KC 80C196KC 80C196KB chip is an important new member of Intel's MCS-96 series of microcontrollers. It is also one of the most powerful products in this series of microcontrollers. It is widely used in various automatic control systems, data acquisition systems and advanced intelligent instruments. The features of the 80C196KC chip are as follows: the oscillation signal frequency reaches 16MHz, the instruction operation speed is faster, 16-bit multiplication is 1.75μs, 32-bit division is 3.0μs; 8 A/D channels can easily realize multi-point voltage and current sampling of the controlled object; communication with the host PC can be realized through the CPU serial port; the newly added 100H~1FFH internal RAM has more flexible application under the vertical window; it has three pulse width modulation (PWM) outputs; 5 more KBs are added on the basis of 80C196KB (KB has already added 6), making program compilation more convenient; 16-bit multiplexed address data/address line can be directly interfaced with PSD, and at the same time, after passing through the latch, the address and data can be connected to the dual-port RAM respectively to realize data transmission between multiple CPUs, etc. For detailed performance parameters and features, please refer to references [1-2]. In the dual CPU system, the main functions of 80C196 include keyboard control, display output, data storage, signal transmission, etc. Due to the complexity of the content involved and the need to interface with many peripherals, a large-capacity, multi-port PSD4000 series chip is used to cooperate with it. Figure 2 shows the circuit diagram of the 80C196KC part.

Although the data and address lines of the CPU can be directly connected to the PSD, in the case of dual-port RAM, the data and address signals must be separated. The required latch is omitted in Figure 2. PSD4235 The PSD4235 chip is the latest PSD4000 series product launched by WSI in 2000. It can adapt to a variety of different microprocessors. It integrates 4M-bit flash memory, 16 output micro-units, 24 input micro-units of CPLD, decoding PLD, 52 individually configurable I/O ports, JTAG serial interface, etc., and has a low-power programmable power management unit that supports power-down mode. The external address allocation of the PSD chip and the logic decoding of each interface are implemented by the dedicated software PSDSOFTTMLITE. For details, please refer to the literature [5-6] or log in to the www.waferscale.com site for inquiry. The use of PSD greatly simplifies the design of hardware circuits, reduces the area of ​​printed circuit boards, and improves the stability of the system. The display part is realized by controlling the graphic LCD module MGLS-12032 through a single-chip microcomputer. The module has two access modes: direct access mode and indirect access mode. This system is based on the indirect access mode. Figure 2 shows the circuit of the indirect access mode. The timing of the display module is realized by programming 80C196. The LCD module MGLS-12032A is two SED1520 cascaded together, one in the master working mode and the other in the slave working mode, which control the left and right half of the display screen respectively. When programming, special attention should be paid to the switching between the two SED1520 in the boundary area when displaying Chinese characters and text. The detailed internal structure of the module and the specific programming implementation method can be found in the literature [7]. [page]

The system has an externally extended serial E2PROM circuit to store some fixed parameters of the system. The chip used is Atmel's AT24C02AT24C02. It can achieve data transmission between the CPU and the CPU by only generating a continuous high and low level sequence through the high-speed input and output channels (HIS and HSO) of the 80C196KC. From the hardware point of view, the chip does not occupy any data bus, the connection is simple and saves a lot of system resources.

1.3 ADMC401 Partial Design

The ADMC401 chip is a controller based on a single-chip DSP, suitable for high-performance control in industrial applications. The chip integrates a 26MIPS (13MHz crystal oscillator) fixed-point core ADSP-2171, with a single instruction execution time of 38.5ns, and its encoding is fully compatible with the ADSP-21xx DSP series. The core has a complete set of peripheral control interfaces to quickly control components in a highly integrated environment; it also contains three calculation units, two data address generators and a program sequencer. The calculation unit includes an arithmetic logic unit ALU, a multiplier/accumulator (MAC) and a barrel shifter. The core also adds instructions such as bit operations, squares, rounding and global interrupt masking. In addition, the ADMC401 chip includes two flexible double-buffered, bidirectional synchronous serial ports. Figure 3 is a functional block diagram of the ADMC401. The ADMC401ADMC401 chip provides 2K×24-bit internal program memory RAM, 2K×24-bit internal program memory ROM, 1K×16-bit internal data memory RAM, 1 high-performance 8-channel 12-bit analog-to-digital conversion ADC system (which can achieve dual-channel simultaneous sampling through 4 pairs of inputs), 1 three-phase 16-bit center-symmetrical PWM generator (which can generate high-precision PWM signals with minimal overhead), 1 flexible incremental encoder interface unit, 2 adjustable frequency auxiliary PWM outputs, 12 I/O digital signal lines, 1 dual-channel event capture system, 1 16-bit watchdog timer, 2 16-bit internal timers, etc.

PSD3xxPSD3xx chips also provide all the components and peripherals needed by many application systems. It is extremely useful to cooperate with PSD for microcontrollers such as 8051, 80196 and 68HC1168HC11. It is also very effective to combine with ADMC401. Considering that the length of the internal program of ADMC401 and the number of interfaces are not as many as those of 80196 controller (80196 needs to complete the human-machine interface implementation, signal transmission, peripheral device interface, etc.), PSD311 (the lowest price 3 series product currently) is used. The boot program loading of ADMC401 chip can be generated through various different states of two pins MMAP and BMODEE. If the pins MMAP and BMODEE are both 0, the ADMC401 chip works in the so-called EPROM boot program mode, in which the dedicated external storage space called "boot memory" allows the chip to be connected to the byte-width EPROM and load the program from the outside through the memory interface when powered on; if the pins MMAP and BMODEE are set to other potentials, different boot modes will be generated; in addition, the 401 chip has a dedicated low-level active signal-boot memory selection BMS (Boot Memory Select) to simplify the interface of the boot memory. The above functions greatly facilitate the interface between the ADMC401 and the PSD. Figure 4 is the interface circuit diagram of the ADMC401 and the PSD311 (some other peripherals are also included in the figure). The connection between the ADMC401 and the PSD311 is almost as simple as its connection with the standard EPROM. Since the bus path is inside the ADM401, the 8 data lines of the PSD311 are not connected to D7~D0 of the ADM401, but to D15~D8C. Also note that the highest bit of the address is provided by the D22 line of the ADM401 (there is no A14 address line in the ADM401). The BMS signal acts as the chip select of the EPROM and is connected to the A19 input of the PSD311. A19 will be defined as the chip enable signal in the PSD program. The ADM401 generates low-active read and write select pulses, which are connected to the RD and WR inputs of the PSD311. These select pulses are used to select the EPROM and RAM of the PSD311 during transmission. The ADM401 has 2K×24 bits of internal program storage space. When using the EPROM bootloader mode (MMAP = 0, BMODE = 0), the external program is downloaded all at once to its internal program storage space through the internal sequencer of the ADMC401 in a 24-bit command format. Of course, the application program may be larger than the internal program storage space of the ADMC401, but if the program executes the following code, the ADMC401 will automatically reboot. The bootloader memory consists of eight pages, each page is 8K bytes long. In a page, every three bytes except the first byte is a null byte. The first byte is the length of the page. Each group of three bytes in two adjacent null bytes contains a 24-bit instruction to be loaded into the DSP internal program memory. That is to say, the 2K×24-bit internal program storage space requires 8K×8-bit external storage space. In the development tool of the ADMC401, there is a program memory PROFIBUS distributor utility program "SPL21". It calculates the correct page length for the user program and sorts the bytes of the user program according to the appropriate protocol, which greatly facilitates the generation of program code. These generated codes can be written directly into PSD311.

2 Application of 80C196KC-ADMC401 Two-Chip System in SVG Device

SVG (Static Var Generator) - Static VAR generator is also called STATCOM (Static Synchronous Compensator). It is an important basic component in the flexible AC transmission system FACTS (Flexible AC Transmission System) technology. Although the cost of SVG device is higher, its flexible dynamic adjustment characteristics, superior compensation effect and smaller equipment size are unmatched by other reactive compensation devices. Many literatures have introduced the principle and development of SVG device. Figure 5 is the structure diagram of SVG device of two-chip system.

The system is divided into three main parts. The first part is the detection and control part composed of two systems: 80C196KC-ADMC401. 80196 is mainly responsible for completing the human-computer interface and sending signals to the upper computer. The high-speed pipeline 8-way A/D sampling port of ADMC401 also provides a guarantee for the rapid acquisition of voltage and current. At the same time, ADMC401 also needs to complete digital filtering calculation, reactive power calculation, and the generation and transmission of PWM control signals. The second part is the inverter circuit composed of IGBT modules. The key component of the SVG device is its inverter bridge circuit, and the dedicated 6-way PWM wave generator integrated in ADMC401 provides a flexible control method. In addition, the inverter circuit part uses Fuji Electric's latest R series IGBT-IPM module 7MBP100RA-120. It combines the previous IGBT unit, drive circuit, protection circuit, etc. in one module, greatly improving the stability of the actual application system, simplifying the difficulty of design, and reducing the size of the device. The third part is a full-wave rectifier circuit composed of power diodes. The rectifier circuit uses the three-phase full-wave rectifier module 6RI100G-160 from Fuji Corporation of Japan. It mainly converts the AC voltage on the three-phase line into DC output, thereby maintaining the stability of the voltage across the DC capacitor and providing a DC power for the inverter circuit. This avoids the situation where the triggering working angle of the inverter needs to be slightly changed to increase and stabilize the voltage on the capacitor. The current detection is completed using the KT100-P type current sensor, and the voltage detection is completed using the CHV-50P voltage sensor. The output display part is the MGLS-12032A liquid crystal module with SED1520SED1520 as the driver chip. The functions of the above components are realized by programming the ADMC401 digital signal processing chip and 80C196KC software. The two-chip system consisting of 80C196KC80C196KC and ADMC401ADMC401 has a wide range of applications and is very suitable for occasions with large computing volume, multiple peripherals and high speed.