Design of multi-machine parallel communication system using single chip microcomputer

1 Introduction

This article introduces a single-chip multi-machine parallel communication system, using 89C51 as the host and multiple 89C2051 as slaves. (89C2051 is a 20-pin 300MIL package with 2K FLASH E2PROM. Except for the lack of two parallel ports, it has all the functions of the MCS-51 series of single-chip microcomputers. Because of its small size and powerful functions, it will be widely used in the field of single-chip microcomputer applications). This parallel communication method is suitable for acting as a communication controller in multi-site, multi-level detection and control systems; it is also suitable for use as a single-chip microcomputer serial port expansion circuit.

Figure 1 Chip logic diagram and four working states

Figure 2 MCU parallel communication principle block diagram [page]

2 Three-state bus buffer register 74HC646

In a multi-machine parallel communication system composed of a single chip, information exchange on the bus generally adopts methods such as PIO (parallel interface) and dual-port registers, and is assisted by a bus arbitration circuit. Commonly used parallel interface chips include 8155, 8255, etc. This article introduces a simple parallel interface circuit, which can not only replace chips such as 8255, but also make the circuit structure simpler and more compact. The circuit consists of a 74HC74 and a 74HC646 (300MIL narrow package).

74HC646 is a three-state bus buffer register, which is actually a dual-port shared memory, but the shared storage area is very small, with only one data input register and one data output register. It is used as a temporary transfer station for single-byte communication data. Every time a byte is transmitted, the master and slave machines shake hands once, take the data away, and then continue the communication of the next byte. 74HC646 can latch the data of the two buses separately, and then exchange data through the internal bus of the chip.

74HC646 has four working states. By controlling these four working states, multiple microcontrollers can use the data port to exchange data, saving the remaining port lines for other work, such as driving LEDs, controlling switches, etc.
The logic diagram of the 74HC646 chip and its four working states are shown in Figure 1.

3 Principle of parallel communication of single-chip microcomputers

The latching of data by 74HC646 only prepares information for completing data exchange. The realization of communication between multiple microcontrollers must also have communication means to enable the microcontroller to understand the working state on the bus and avoid bus conflicts. Four-wire handshake communication is used here: two lines are sent from the sender to the receiver to notify the receiver that the data is ready (TFNE*, RFNE* in Figure 2); two lines are sent from the receiver to the sender to notify the sender that the data has been received (TFNF*, RFNF* in Figure 2). The communication signal is generated by the 74HC74 circuit. The block diagram of the principle of parallel communication of single-chip microcomputers is shown in Figure 2.

4 Multi-machine parallel communication protocol

The parallel communication microcontroller above does not have a blocking circuit to prevent the master and slave from writing or reading numbers to the 74HC646 at the same time. Therefore, each single machine must control its next operation according to the status information during bidirectional transmission, that is, to communicate. Only by coordinating the software and hardware communication protocols can errors be avoided and competition conflicts with the 74HC646 will not occur. Therefore, in addition to the communication circuit mentioned above, the following protocol must be followed when compiling the software:

When the host sends data to the 74HC646, the 74HC646 receiving register must be empty.

The data transmission between the host and the slave must pass through the 74HC646. The protocol does not allow both parties to operate the 74HC646 at the same time, and their operations must be controlled according to the status information.

5 Communication protocol format and execution process

5.1 Information format

In the asynchronous communication transmission of parallel communication, there are also frame type and format issues. A frame format similar to serial communication can be used:

feature word

length

data 1

data 2

...

check code

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5.2 Execution process of communication protocol

The following is an example of the execution process of the communication protocol using the detection method.

5.2.1 The process of the host writing data to the slave: (host writes, slave reads)

The host writes data to the 74HC646, then notifies the slave that there is data, and the slave reads data from the 74HC646.

① The host reads the status bit and detects whether the TFNF* bit is zero.

② If TFNF*＝1, the host waits temporarily; if TFNF*＝0, the host writes data to the 74HC646, making TFNF*＝1, and TFNE*＝0 at the same time.

③ The slave reads the status bit and detects whether the TFNE* bit is zero. If TFNE*＝1, ​​the slave waits temporarily; if TFNE*＝0, the slave reads data from the 74HC646, making TFNE*＝1, ​​and TFNF*＝0 at the same time.

④ The host detects whether the status bit TFNF* is zero again. If it is "0", it means that the slave has taken the data from 74HC646, and the host can send the next data.

5.2.2 The process of the host reading the slave: (slave writes, host reads)

The slave writes data to 74HC646, and then notifies the host that there is data. After receiving the signal, the host takes the data from 74HC646.

① The slave reads the status bit and detects whether the RFNF* bit is zero.

② If RFNF*=1, the slave waits temporarily; if RFNF*=0, the slave writes data to 74HC646, making RFNF*=1, and making RFNE*=0 at the same time.

③ The host reads the status bit and detects whether the RFNE* bit is zero. If RFNE*＝1, ​​the host waits temporarily; if RFNE*=0, the host reads data from 74HC646, making RFNE*＝1, ​​and making RFNF*＝0 at the same time.

④ The slave detects again whether the status bit RFNF* is zero. If it is "0", it means that the slave has taken the data from 74HC646 and the host can send the next data.

6 Flowchart (Detection Method)

The program flow using the detection method is shown in Figure 3.

Figure 3 Flowchart of the program using the detection method

If the interrupt method is used, only slight modifications need to be made to the execution process and the flowchart.