Serial EEPROM X24128 and its interface with AT89C51 and programming

X24128 is a CMOS serial communication EEPROM produced by Xicor Corporation of the United States. The internal structure is a 16k byte 8-bit array. X24182 can connect 8 pieces in parallel on a 2-wire bus at the same time, and has software and hardware write protection functions. The highest address unit (FFFFH) in the chip is a write protection register. By writing different data, three different forms of write protection can be performed: software write protection, block lock selection protection and programming hardware write protection. The highest clock frequency of serial communication on a 2-wire bus is 400kHz. In addition, it also has input and output noise elimination and suppression functions. And low power consumption, its read state working current is less than 1mA, the write state working current is less than 3mA, and the static current is less than 1uA. There are three types of working voltages: 1.8V-3.6V, 2.5V-5.5V and 4.5V-5.5V for selection. There are two types of write modes: write by byte and write by page, and each page is 32 bytes.

1. Pin Description

X24128 has three package types: 14-SOIC, 16-SOIC and 8-PDIP. Figure 1 is the appearance of the 8-PDIP package. The function of each pin is as follows:

Vcc, Vss: positive and negative input terminals of the power supply;

SCL: Serial clock input terminal, used to control the input and output of data;

SDA: Common pin for serial data input and output. Drain output, can form a line or logic relationship with the output of the SDA pin of other devices. Because it is a drain output, a pull-up resistor must be connected when in use;

WP: Hardware write protection input pin. When the WP pin is connected to a high level and the WPEN bit of the write protection register is written to 1, the write protection register implements write protection. At this time, the block-locked storage array can no longer be rewritten by the program. When write protection is not required, the WP pin is connected to a low level;

S0, S1, S2 are device selection input terminals. Up to 8 X24128s can be connected in parallel on the serial communication bus, and they can share the bus in time. In the input address, when the data of the first byte (device address) matches the input pins S0, S1, S2 of the device, the device is selected and can communicate serially with the CPU. If it does not match the input pins of the device, it is in a waiting state. [page]

2. Address selection

The internal EEPROM of X24128 consists of 16k×8 bits, and the address of this 16k data unit is 0000H-3FFFH. The address of the write protection register is FFFFH. Each address can be divided into the high-order byte BYTE1 and the low-order byte BYTE0. In addition to the data unit address, there is also a device address. In the device address, the high four bits must be 1010, which is the identification code of X24128. The three bits S2, S1, and S0 are the address code of the selected device, and they must be consistent with the input pins S2, S1, and S0 of the selected device. For example, if the S2 pin of the selected device is connected to Vcc, and the two input pins S1 and S0 are connected to Vss, the device address should be 1010100R/WB. Bit Bit is the read and write selection bit. When the bit is 1, read is selected; when the bit is 0, write is selected.

3. Write protection register

The write protection register is a readable register with the following format: The status of each bit can be written by the program. The function is described as follows:

WEL: EEPROM array write enable latch. When WEL=1, the write enable latch is set and write operations can be performed. When WEL=0, the write enable latch is reset and all write operations are rejected.

RWEL: Write enable latch for "write protection register". When RWEL=1, the "write protection register" can be rewritten; when RWEL=0, the write enable latch is reset and rewriting is prohibited.

At power-on, both WEL and RWEL are reset.

BL1, BL0: EEPROM array block lock protection bit. The entire EEPROM array has three lock modes: when BL1, BL0=00, the entire array is not block locked; when BL1, BL0=01, the array with address 3000H~FFFH is block locked; when BL1, BL0=10, the array with address 2000~3FFF is block locked; when BL1, BL0=11, the array with address 0000H~3FFFH is block locked.

WPEN: Write protection enable bit. When the WPEN bit is written to 1 and the WP pin of the device is connected to Vcc, the hardware write protection is enabled. When the WPEN bit is reset or the WP pin is connected to Vss, the hardware write protection is no longer enabled. Hardware write protection can provide convenience for users to implement write protection operations in actual application operations of the entire system.

The memory array that is block locked by BL1 and BL0 is not affected by hardware write protection. The area range of the block lock protection array can only be changed by changing the values ​​of BL1 and BL0. However, changing the values ​​of BL1 and BL0 is subject to the constraints of the RWEL bit. The change of the RWEL bit is also subject to the constraints of hardware write protection. The array without block lock protection is not subject to the constraints of hardware write protection, so it can be written.

Without hardware write protection, rewriting BL1 and BL0 can be done in the following three steps:

1) Write 00000010 to the FFFFH address to make WEL=1;

2) Write 00000110B to the FFFFH address to make RWEL = 1;

3) Write X00XX010B to the FFFFH address and set RWEL = 0. This will write-protect the register. If RWEL = 1 in step (3), rewriting the register will be invalid. The register will still maintain the status of step (2).

4. Read and write timing

Before performing read and write operations, set the start state first. The method is to command the SCL bus to maintain a high level and set a jump from high level to low level on the SDA bus. At the end of communication, it is necessary to set an end state, that is, to protect the SCL bus at a high level and set a jump from low level to high level on the SDA bus. After setting the end state, the device leaves the communication state.

The change of communication data on the SDA bus must be carried out when the SCL bus is in a low level state. When the SCL bus is in a high level, the data is in a hold state.

During the communication process, each time the device receiving data receives 8 bits of data effectively, it sends a negative pulse response signal to the device sending data. During the fixed operation process, each time X24128 receives 8 bits of data (including receiving 8 bits of address data), it generates a negative pulse on the SDA bus, and the width of the pulse continues until the end of the 9th clock pulse signal. During the read operation process, each time the CPU receives 8 bits of data sent by X24128, it sends a negative pulse on the SDA bus to indicate that the read is valid, and then X24128 can continue to send data. If X24128 does not receive a response signal, it stops sending data until it receives the end signal, and the communication ends. [page]

4.1 Byte Write Timing

When writing a byte of data to a unit in the unlocked part of the X24128 internal storage array, first set the start state, then send byte 1 and byte 0 of the device address and data address in sequence. After each 8-bit address byte is received by X24128, it uses the 9th clock pulse to send a response signal. After the CPU receives the third response signal, it sends 8 bits of data and receives the response signal, and finally sets the end state. After receiving the end signal, X24128 starts the internal write process of writing the received data into the EEPROM array. During the internal write process, it does not respond to any external input signal, and the SDA pin outputs a high impedance state.

4.2 Write Timing by Page

When the CPU writes data to X24128, it can be written in pages, each page includes 32 bytes. The page writing method is the same as byte writing at the beginning, but each time a byte of data is written, the internal address pointer of X24128 automatically increases by 1 before continuing to write data, and there is no need to write the address again. After the highest address of this page is written, the address pointer automatically returns to the lowest address of this page. If data is continued to be written, the data that has been written will be overwritten. Only after sending the end signal to X24128, X24128 will stop receiving data and start the internal writing process.

4.3 Read current address data

If you want to read the data of the unit currently pointed by the internal address pointer of X24128, you only need to send the start signal and device address ( bit is 1) to X24128 and receive the response signal, then you can receive the data of the current address sent by X24128. After receiving, send the end signal. After X24128 sends the data, the address pointer automatically increases by 1.

4.4 Read data from any address

First send the address of the data to be read to X24128, so that it becomes the address pointed by the current address pointer. Write 0 to the bit of the device address, and then read the data in the same way as reading the current address data.

4.5 Continuous reading of data

Continuously reading data is like reading data at any address. Set the first address of the data to be read continuously as the current address. After receiving the first byte of data, instead of sending an end signal, send an acknowledge signal. X24128 continues to send the second byte of data after receiving the acknowledge signal. As long as the CPU sends an acknowledge signal after receiving a byte of data each time, X24128 will continue to send the next byte of data. After sending the data at the highest address of the entire storage array, the address pointer will return to unit 0000H. If you continue to send an acknowledge signal, X24128 will continue to send data from unit 0000H. The transmission will only be terminated when the end signal is received. [page]

5. Interface circuit and programming

The interface circuit between X24128 and AT89C51 is shown in Figure 2. Up to 8 X24128s can be connected in parallel on a 2-wire bus. The P1.0 port line is used as the clock signal output, and the P1.1 port line is used as the data input and output. The bus is connected to a 4.7kΩ pull-up resistor. The following example takes the data of AT89C51 register R2 written into the 1000H address of X24128 (1). Assuming that the 1000H address is not write-protected, the programming is as follows: