Problems and solutions in parallel communication between two single-chip microcomputers

1 Introduction

This system is mainly used in dual-CPU computer embroidery machines. In order to reduce the control burden of the lower computer and better complete the embroidery of the pattern. Secondly, prepare for the next offline work (that is, prepare for the embroidery of the next pattern while the machine is embroidering), so that the work efficiency can be further improved. Because the system encountered the problem of program runaway in the initial development, it was proposed to use CPLD (programmable logic device) to solve the communication interference problem.

The CPLD used in this system is the ATF1540AS device produced by ATMEL. This device is a high-performance, high-density composite programmable logic device, referred to as CPLD. It uses ATMEL's electrically erasable memory technology, has 64 logic macro cells and 68 I/O ports, and can be easily combined with multiple TTL, SSI, MSI, LSI and classic PLDS. Each macro cell includes five parts: product term and product term multiplexer, OR/XOR/CASCADE logic, trigger, output selection and enable, and input logic array. The enhanced routing switch of ATF1504AS increases the available gate count and improves the success rate of pin latch design modification.

Figure 1. Block diagram of two-machine communication

2 System Structure

The system's CPU uses W77E58, and the communication interface is composed of ATF1504AS. The system block diagram is shown in Figure 1.

2.1 Problem Statement

In order to achieve a good human-computer interface interaction function, the computer embroidery machine adopts a upper and lower computer mode, where the lower computer mainly controls the embroidery action and the upper computer mainly tracks the pattern. In order to realize embroidery and embroidery tracking on the LCD screen at the same time, the single CPU mode has system resource overdraft, and it will be very difficult for the CPU to process data. Therefore, the dual CPU working mode is proposed, but it also brings a problem - the communication problem of the dual CPU.

2.2 Solution

(1) Using serial communication mode
Advantages: In the multi-machine mode composed of single-chip microcomputers, the serial interface mode is the most commonly used. The serial communication mode interface circuit is simple and can easily realize long-distance transmission. The anti-interference ability is relatively good.
Disadvantages: The data transmission is slow and not suitable for real-time data transmission. When the data transmission requirements are high, it is easy to cause bottlenecks.
(2) Using parallel communication mode
Advantages: Parallel communication transmits data quickly and is suitable for real-time control.
Disadvantages: Poor anti-interference ability, not suitable for long-distance transmission, and the maximum distance does not exceed 5m.
Since this system has high requirements for the real-time performance of data transmission, and the distance between the upper and lower computers does not exceed 3m, appropriate anti-interference measures can fully meet the system requirements, so it is determined to use parallel communication mode.

2.3 Specific measures

(1) ATF1504AS (programmable logic device) is used for parallel communication to reduce the noise interference caused by the stray capacitance generated by discrete devices.
(2) A Schmitt circuit (74LS14) is added to the input data end to filter out the coupling noise on the external transmission line. This improves the anti-interference performance of the bus reception.
(3) The use of a three-state gate drive method can improve the anti-interference ability of the bus, because the three-state gate has three state outputs, namely the so-called low-resistance high level, low-resistance low level, and high-resistance state (forbidden state). Since the input of the three-state gate has three states, the burden on the signal source of the three-state gate is reduced. This is conducive to improving speed and anti-interference ability.

3 Dual CPU Communication Principle Design

3.1 Dual CPU Communication Schematic Diagram

As can be seen from the dual CPU communication schematic diagram in Figure 2, the 74LS14 Schmitt circuit and 74LS244 three-state gate driver are connected to the input interface to improve the anti-interference ability. The 74LS14 Schmitt circuit is connected to the handshake signal lines of SRZB, SCYX (host computer) and SRZB, SCYX (slave computer) to improve the anti-interference ability.

Figure 2 Schematic diagram of two-machine communication

3.2 ATF1504AS internal schematic diagram

Due to limited space, only the internal schematic diagram of ATF1504AS of the upper computer is listed as Figure 3. The internal schematic diagram of ATF1504AS of the lower computer is similar to this.

Figure 3 ATF1504AS internal schematic diagram

4 System Working Principle

4.1 Host computer input data

As shown in Figure 3. Before inputting data, initialize U2 (D flip-flop) through U1 (74173), that is, input a rising edge pulse to the CLRN end of U2 to clear U2. At this time, the SRYX end of the host computer is low level, and the ZDQQ end is high level. At this time, it is ready to receive data. When the lower computer receives the low level output from the SRYX end of the host computer, it can send data to the latch, and then output a rising edge pulse to the SRZB end of the host computer, the Q end (SRYX end) of U2 outputs a positive pulse, and the ZDQQ end outputs a negative pulse through the inverter. When the host computer detects that the ZDQQ end is low, it takes out the data on the data line. Then initialize U2 through UI, complete the reading of one byte, and prepare for reading the next byte. The waveform of the host computer input data signal is shown in Figure 5.

Figure 4 Signal waveform when the host computer outputs data [page]

Figure 5 Signal waveform when the host computer inputs data

4.2 Host computer output data

As shown in Figure 3, before outputting data, initialize U1 (74173) to U3 (D flip-flop), that is, input a rising edge pulse to the PRN terminal of U3 to set the output of U3 to 1. At this time, the SCZB terminal of the host computer outputs a low level through the inverter, and the Q terminal of U3 is a high level. At this time, it is ready to send data. When the SCYX terminal of the host computer receives the input rising edge pulse, the Q terminal of U3 is a low level. When the CPU detects that the Q terminal is a low level, it can send data to the latch, and then output a rising edge pulse to the SRZB terminal of the lower computer through the SCZB terminal of the host computer. Indicates that the data has been sent, and then initialize U1 to U2. Complete the output of one byte and prepare for the output of the next byte. The waveform of the host computer output data signal is shown in Figure 4.

5 Software Design

5.1 Program flow design

FIG. 6 shows an input data flow chart, and FIG. 7 shows an output data flow chart.

Figure 6 Data input process

Figure 7 Data output program flow chart

5.2 Partial Program Listing

(1) Data input program list
ORG 0000H
JMP START
ORG 0003H
JMP RESEVE
START: MOV TCON,#0 ;Set interrupt INT0
MOV TMOD,#11H
CALL SZSRDK ;Set input port
MOV IE,#81H
MOV IP,#1 ;Open interrupt
..
..
..
RESEVE: CLR EA ;Open interrupt
PUSH PSW
PUSH DPH
PUSH DPL
RESEV1: JB ZDQQ,RESEV1
;Judge whether ZDQQ is low
MOV DPTR,#ADDR0
;Address of U5 (input data port)
MOVX A, @DPTR
..
..
CALL SZSRDK
POP DPL
POP DPH
POP PSW
SETB EA
RETI
SZSRDK: CLRN EQU 2CH.0
CLR CLRN ;
MOV DPTR,#ADDR1
;For the address of U1
MOV A,2CH
MOVX @DPTR,A
SETB CLRN
MOV A,2CH
MOV DPTR,#ADDR1
MOVX @DPTR,A
RET
(2) Output data program list
SEND: MOV DPTR,#ADDR3
MOVX A,@DPTR
JB ACC.0,SEND
;For the Q terminal output of U3
MOV DPTR,#ADDR4
;For the address of U4 (output port)
MOVX @DPTR,A
CALL SZSCDK
RET
SZSCDK: PRN EQU 2CH.1
SETB PRN
MOV DPTR,#ADDR1
;For the address of U1
MOV A,2CH
MOVX @DPTR,A
CLR PRN
MOV DPTR,#ADDR1
MOV A,2CH
MOVX @DPTR,A
RET

6 Conclusion

The design uses the AT1504AS device, which realizes the softwareization of hardware design, facilitates hardware design, shortens the design cycle, reduces the design cost, and is also very convenient to use. After taking the above measures, the system has met the initial design requirements. The product has been put on the market and the market response is good.