Design of high-speed data acquisition system based on MAX114

1 Introduction

Data acquisition technology is a very important branch of information science. It studies the conversion, acquisition, storage, processing and display of information data, and plays a huge role in signal processing, intelligent instruments and industrial automatic control. For example, in the industrial production process, it is often necessary to detect and monitor various process parameters such as humidity, temperature, pressure, flow, etc. at any time, and at the same time, the detected data must be transmitted to the host computer in a timely manner to realize random query of parameters, storage and processing of information, timely adjustment of control schemes, and improve production efficiency and product quality.

However, in many other fields such as radar communication, geographic information, image transmission, military industry and medical chemical industry, in order to capture, collect, store, process, transmit and reproduce the instantaneous analog signals (similar to pulse signals), higher requirements are put forward for data acquisition speed and efficiency. This paper uses the single-chip microcomputer 89C51 as the main control to realize the high-speed acquisition, storage and reproduction of analog signals. In the application, the single-chip microcomputer only transfers the signal without processing the data. After the collected digital signal is transmitted to the DA converter, the DA converter restores the signal to an analog signal.

2 Hardware Composition

The designed scheme is mainly used for instantaneous signal acquisition, and the A/D conversion chip selected is required to have a relatively fast conversion speed. After careful consideration, MAX114 is selected. The instruction execution time (us level) of the 89C51 microcontroller is often not synchronized with the conversion time of the AD conversion chip ^[1] . Therefore, a high-speed cache IDT72041 is added between the microcontroller and the AD converter, and the high-speed cache is used to connect the microcontroller and the AD converter. The overall structure block diagram of the system is shown in Figure 1.

Figure 1 System overall structure diagram

In practical applications, instantaneous continuous analog signals must be converted into digital signals that are easy to store and analyze. In this process, the distortion of the analog signal should be avoided as much as possible, which is closely related to the conversion accuracy and conversion speed of the AD conversion chip. When the frequency of the analog signal is very high, the conversion speed of the AD chip is particularly important. The MAX114 chip has certain requirements for the input analog voltage, and the input analog voltage must be amplified to meet the requirements of the AD conversion chip ^[2] . The preamplifier circuit of MAX114 is shown in Figure 2:

Figure 2 Amplification and filtering circuit

High-pass filtering only allows signals of a certain frequency to pass through, eliminating the influence of noise. The bypass capacitors connected to the REF+ and REF- pins of MAX114 eliminate interference. MAX114 is a four-channel A/D chip, and we only need one channel to convert data, so A1 and A2 must be connected to digital "0". Select the mode "0" state to convert data as needed, and pin "5" MODE must also be connected to digital "0". Its truth table is shown in Table 1: www.51kaifa.com

Table 1 MAX114 truth table

The AD conversion chip MAX114 transmits the converted digital signal to the cache IDT72041. The working clock of MAX114 is provided by the clock pulse provided by the internal clock circuit, and the cache write control signal is also controlled by the "INT" of the chip. After the AD chip completes the conversion, "INT" generates a low level, which is transmitted to the cache chip. The data is written into the cache and saved according to the first-in-first-out rule. Only when the cache pin (FF) is high and (EF) is low, the data converted by AD can be written ^[3] .

The IDT72XX series is a first-in-first-out (FIFO) memory chip launched by IDT. It has dual-port input and output, fast data acquisition and transmission speed, and first-in-first-out characteristics, which can meet the requirements of high-speed data transmission ^[4] .

The cache IDT72041 has such a feature: when the cache chip is full, the cache chip will no longer accept external write signals, and the full bit FF of the cache IDT72041 will become low, and the external interrupt of the microcontroller will be triggered. After receiving the interrupt signal, the microcontroller runs the chip selection program, and the second cache starts to read the A/D conversion data. Similarly, when the data in all cache chips are fully written, the microcontroller transfers the data in the cache through the application program and then processes it. After all the data in the cache is processed, the A/D conversion is restarted to start data collection.

In order to ensure the continuity of data collection and to collect enough data, a large storage space must be available to store data. For this purpose, the IDT72041 chip is expanded to 8 pieces in this system ^[5] . The first chip in the expansion is represented by the FL/RT terminal being grounded, and the FL/RT terminals of other chips are connected to a high level. The "XO" terminal of each chip must be connected to the "XI" terminal of the next chip. The "EF" flag of each chip is "OR"ed to form a new empty flag, and the "FF" terminal of each chip is also "OR"ed together to form a new full flag. RT and HF do not work in the expansion of word depth. The method adopted here is to connect the "FF" terminals of the 8 chips to the P2 port of the microcontroller respectively, and the microcontroller controls the full write.

In the design, when the 4K storage space of the IDT cache chip is full, the cache pin "FF" is low, and the data converted by MAX114 can no longer be written. At the same time, FF sends an interrupt request to 89C51. After receiving the interrupt signal, the microcontroller uses the P0 port to realize data transmission with the cache chip, and then the microcontroller performs preliminary processing on the data stored in IDT72041. After the chip selection of the microcontroller P3.6 port (WR), the processed data is transmitted to DAC0832 ^[6] .

In the hardware circuit, the microcontroller controls IDT72041 and DAC0832. When MAX114 starts sampling, it uses the D0-D7 data lines and write control port WR in IDT72041. When the data sampling is finished, that is, the data has been stored in IDT72041, the microcontroller will read the data from IDT72041, using the Q0-Q7 lines and read control port. In actual use, the signal crosstalk problem is solved by setting different levels of the QE pin and the /DIR pin. The three-state function can be realized by setting different levels of the QE pin, and the /DIR pin determines the direction of signal transmission.

3. System Software

3.1 Program Functions www.51kaifa.com

The function of this program is to realize the communication between AD chip MAX114 and cache IDT72041 and control the sampling frequency. Each function is completed by a process ^[6] . The main body of the program is divided into five parts: initialization of the microcontroller and setting of peripheral devices, judgment of the full flag of the cache and loop of this instruction, chip selection of the cache and transfer of cache data to microcontroller register A, chip selection of DAC and transfer of data in the temporary register to DAC, judgment of whether the cache is empty and jump.

3.2 Implementation of each part of the program

The first part is the initialization of the microcontroller and the peripheral devices, mainly the setting of IDT72041. It starts with setting all the ports of 89C51's P0, P1 and P2 to 1, then clears P1.1 to "0" to reset IDT72041, and clears P1.1 to "0" to select the MAX114. The instructions are as follows:

START：SETB P0

SETB P1

SETB P2

CLR   P1.0

CLR   P1.1

The second part is mainly to determine whether the cache is full. The input analog signal enters the system, is amplified and rectified by the amplifier circuit, and then enters the A/D (MAX114) for conversion. Since the INT pin of the A/D chip will generate a low level after each conversion, this low level drives the cache (IDT72041) to write data. Since 8 caches are used, there will be a problem of which cache the data will be written to first. In order to improve the processing efficiency of the microcontroller, the XO terminal of the previous chip is connected to the XI terminal of the next chip in hardware, the FL/RT of the logic "1" chip is grounded, and the FL/RT of other chips is connected to a high level. In this way, the 8 cache chips can be combined into a storage entity. In this way, data will be written from the first chip to the last chip. The full end "FF" of the 8 caches is connected to the P2 port of the single-chip node to determine whether each cache is full. In terms of hardware connection, the 8 caches have formed a whole storage body, so in terms of software, it is only necessary to determine whether P2.7 is "0" to determine whether the cache is full ^[7] , that is:

ST：JNB   P2.7, ST

The third part determines whether the cache is full. If it is full, the A/D conversion is terminated and all the converted data will be stored in the cache. The instructions are as follows: www.51kaifa.com

SETB P1.1

The fourth part selects the DAC chip and transfers the data in the temporary register to the DAC. The first address is stored in the DPTR data pointer register, and the data is sequentially read from the cache and stored in the external RAM. After preliminary processing by the microcontroller, it is transferred to the DAC. The instructions are as follows:

MCADTS：MOV   DPTR, # 7000H

CLR    P2.6

MOVX A,@DPTR

MOV DPTR, #5000H

CLR    P2.0

MOVX @DPTR,A

The fifth part determines whether the cache is empty. If it is not empty, it will continue to read data. Otherwise, the program jumps to the initial position and repeats the above process to achieve continuous data collection and restoration. The instructions are as follows:

SA： JNB INT1, MCADTS

SJMP START

Conclusion:

The author's innovation points are:

This system uses a simple MCS-51 single-chip microcomputer to realize complex data acquisition and restoration circuits. During the operation, the application system is divided into modules according to its functions, the circuits are welded and debugged, and simulation tests are performed. The system design has a simple circuit and good reliability, achieving the purpose of high-speed data acquisition.

References:

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