Expansion of external data memory based on P0 port of 51 single chip microcomputer

With the continuous improvement of the computing speed and processing power of single-chip microcomputers, they are more widely used in various fields. However, with the continuous expansion of its application field and the continuous improvement of its integration, its internal resources can no longer meet the actual needs, and it is often necessary to expand its internal resources. The classic expansion method is mainly to expand the data or program memory through the address bus, data bus, namely P0, P2 port, and control lines ALE, *****, etc. The maximum addressing space can reach 64KB, but this method occupies more ports and cannot meet the needs in some cases. Here, taking the MCS-8051 series of single-chip microcomputers as an example, a new off-chip data memory expansion method is introduced. Only 10 ports, namely P0, P1.6 and P1.7 of the single-chip microcomputer, can realize the expansion of 256 KB data memory.

1 Overall design idea
The internal storage space of the MCS-8051 single-chip microcomputer is 256 B, with 4 I/O ports, namely P0, P1, P2 and P3. In actual applications, its internal storage space often cannot meet the needs, and it is often expanded outside the chip. Different from the classic expansion method, the P2 port is not used here. Only the P0 port is connected to the address line and data line of each memory to form the address bus and data bus. At the same time, the three ports P0.0, P0.1 and P0.2 of the PO port are led to the input end of the decoding device. After decoding, they are used as the chip selection control lines of the data storage device, and together with other control ports of the single-chip microcomputer, they form a control bus. Thus, the expansion of the 256 KB data storage outside the single-chip microcomputer is realized through the three buses of data bus, address bus and control bus.
The PO port of the single-chip microcomputer has the functions of address bus, data bus and control line. The address signal, data signal and chip selection control signal are transmitted by software in time-sharing.

2 Hardware interface circuit design
The expansion circuit of MCS-805l single-chip microcomputer and multiple 62256 data storage devices mainly consists of 8 62256 data storage devices, 3 74IS373 latches and 1 74LS138 decoding device. The 62 256 data memory is a 32 KB static random access memory, with a chip select signal input line, a write enable signal input line, a read enable signal input line, A0 to A14 as address input lines, and D0 to D7 as bidirectional tri-state data lines. The state of the control pin level of this memory device in different operation modes is shown in Table 1. 74LS373 is an 8D flip-flop with tri-state buffer output, OE is the enable terminal, and G is the control terminal. Its functions are shown in Table 2.

Figure 1 is the hardware connection circuit between the MCS-8051 microcontroller and multiple 62256 data memories. The P0 port of the microcontroller is connected to the input ports of the decoder 741S138, latches 74LS373-0 and 74LS373-1 to transmit address information and control information. At the same time, the P0 port is also connected to the data line of the data memory to transmit data information. P1.6 is connected to the control terminal G of the latch 74LS373-2, P1.7 is connected to the control terminal G of the latch 74LS373-1, and ALE is connected to the control terminal of the latch 74LS373-0. Therefore, under the joint action of the three ports P1.6, P1.7 and ALE, the time-sharing transmission of address information and data information can be realized. T0~T7 are 8 62256 data memories, which constitute an off-chip 256 KB storage space.

3 Software Design
3.1 Software Design of Data Memory Expansion
The main idea of ​​software design for the MCS-8051 MCU's 256 KB external data memory expansion is how to establish a connection between the MCS-8051 MCU and the external memory unit to be accessed, so as to realize the information transmission between the two. When the MOVX instruction is executed, the address information is latched at the same time, and then the data is transmitted. Its read and write cycles are very short, but it occupies more ports. In order to save port resources, the address information can be transmitted in time-sharing. Figure 2 shows the process of the MCU reading and writing external data memory. Unlike the MOVX instruction, when the MCU accesses the external memory unit, it first sends the address information of the external memory unit into the latch in time-sharing and latches it, and then reads and writes the external data memory unit. These are two completely independent processes. This feature greatly saves port resources, but the read and write cycles are longer. [page]

3.2 Analysis of software examples for data memory expansion
Analysis of the software design for data memory expansion shows that software design plays an important role when the MCU reads and writes the off-chip data storage unit through the P1 port. The following example introduces the process of the MCU accessing the off-chip data storage unit.
The following program segment first reads the content of the off-chip memory unit 000000H into the on-chip memory unit 30H, and then writes the content of the on-chip memory unit 30H to the off-chip memory unit 077FFFH. In the program, the on-chip storage units 20H, 21H and 22H are first defined as address information storage units. 20H is the high 8-bit address information storage unit, and only the low 3 bits are valid; 21H is the middle 8-bit address information storage unit, and the low 7 bits are valid; 22H is the low 8-bit address information storage unit, and all 8 bits are valid. Therefore, its addressing space is 000000H～007FFFH, 010000H～017FFFH, 020000H～027FFFH, 030000H～037FFFH, 040000H～047FFFH, 050000H～057FFFH, 060OOOH～067FFFH and 070000H～077FFFH, totaling 256 KB. MOVR and MOVW are read and write subroutines respectively.


From the analysis of the program, it can be seen that the expansion of large-capacity data storage outside the chip can be realized by using only P0 port and several other few control ports, mainly because P0 port has the functions of address line, data line and chip selection control line, and this function is realized by software, that is, time-sharing transmission of address information, data information and control information. The specific data transmission process can be seen from the two subroutines of MOVR and MOVW. In addition, during the programming process, each time the content of the external memory is read or written, the address information is written to the three units of DPHH, DPTRH and DPTRL, and then the subroutines MOVR and MOVW are called to implement the read or write operations of the off-chip data memory.

4 Conclusion This paper
introduces the expansion method of the 256 KB off-chip data memory of the MCS-8051 microcontroller. Its main features are large expanded storage space, few occupied ports, and parallel data transmission. In the case of many peripheral devices, limited ports cannot meet the requirements, or when the storage space is difficult to meet the requirements, this expansion method can be fully adopted. In addition, if the hardware connection part between the microcontroller and the data storage device is slightly modified, the off-chip 256 KB can be directly accessed, and the two access methods can be completely independent. If the 256 KB storage space still cannot meet the actual needs, it is better to decode all 8 bits of the high-order address storage unit. 256 chip selection control ports can be obtained, so the original 8-chip data memory can be increased to 256 chips. In this way, the off-chip storage space can reach 8 MB. It fully meets the demand. Moreover, according to this principle, the original 3 address storage units can be changed to 4 address storage units or more to increase its storage space. However, its read and write cycles will also be longer. Therefore, it is necessary to make comprehensive considerations based on the actual situation and ultimately optimize the hardware and software of the microcontroller.