Active Clamp Flyback Soft Switching Circuit Design-EEWORLD

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Flyback converters are widely used in low-power applications due to their simple circuits. However, due to the presence of transformer leakage inductance, excessive voltage stress is caused on the switch tube. The leakage inductance energy of ordinary RCD embedded flyback converters is consumed in the embedded resistor R, and the magnitude of the voltage stress on the switch tube depends on the magnitude of the energy consumed in the embedded resistor. The more energy consumed in the embedded resistor, the lower the voltage stress of the switch tube, but it also affects the efficiency of the entire converter. Therefore, ordinary RCD embedded flyback converters always have a contradiction between the voltage stress of the switch tube and the efficiency of the entire converter.

Miniaturization is the goal of current power products. Increasing the switching frequency can reduce the size of components such as inductors and capacitors. However, the bottleneck of increasing the switching frequency is the switching loss of the switching device, so soft switching technology came into being. Generally, to achieve a relatively ideal soft switching effect, one or more auxiliary switches are required to create soft switching conditions for the main switch, and it is hoped that the auxiliary switch itself can also achieve soft switching.

This article introduces an active embedded Flyback soft switching circuit, which can not only achieve ZVS, but also solve the problems existing in the aforementioned ordinary RCD embedded Flyback converter.

1 Working Principle

The circuit is shown in Figure 1. Its two switches S1 and S2 are complementary to each other, and there is a certain dead zone in the middle to prevent common conduction. The transformer excitation inductance Lm is designed to be large, so that the circuit works in the continuous current mode (CCM), as shown in the iLm waveform of Figure 2. The inductance Lr is designed to be small (Lr?Lm), so that the current flowing through Lr can be reversed within one cycle, as shown in the iLr waveform of Figure 2. Considering the junction capacitance and dead time of the switch, one cycle can be divided into 8 stages, and the equivalent circuit of each stage is shown in Figure 3. Its working principle is as follows.

1) Phase 1〔t0, t1〕In this phase, S1 is turned on, Lm and Lr are connected in series to bear the input voltage, and the current flowing through Lm and Lr increases linearly.

V2=Vin(Lin/Lm+Lr) （1）

Since Lr?Lm, equation (1) can be simplified to

V2≈Vin (2)

2) Phase 2〔t1, t2〕At t1, S1 is turned off, and the currents on Lm and Lr charge the output junction capacitance Cr1 of S1, while discharging the output junction capacitance Cr2 of S2. At t2, the drain-source voltage of S2 drops to zero, and this phase ends.

Figure 2

3) Phase 3〔t2, t3〕When the drain-source voltage of S2 drops to zero, the parasitic diode of S2 turns on, clamping the drain-source voltage of S2 at zero voltage. Lr and Lm are connected in series to resonate with the clamping capacitor Cclamp, and the voltage vc on Cclamp rises slowly, and the voltage on v2 also rises slowly.

v2=(Lm/Lm+Lr)vc （3）

4) Phase 4〔t3, t4〕At t3, the gate of S2 changes to high level, and S2 is turned on with zero voltage. The current flowing through the parasitic diode flows through S2. During this period, Lr and Lm are still connected in series to resonate with the clamping capacitor Cclamp, and v2 rises slowly.

5) Phase 5〔t4, t5〕At t4, v2 rises to a certain voltage to turn on the secondary diode D, and v2 is clamped at -NVo. Lr resonates with Cclamp. Under the condition that the current of Lr is reversed at t5, its resonant period should satisfy

In the formula, toff is the off time of the main switch S1 in one cycle. At t5 in

Figure 3

, S2 is turned off and this stage ends.

6) Phase 6〔t5, t6〕At t5, the current direction on Lr is negative. Part of this current discharges the output junction capacitance Cr1 of S1, and the other part charges the output junction capacitance Cr2 of S2. At t6, the drain-source voltage of S1 drops to zero, and this phase ends.

7) Phase 7〔t6, t7〕When the drain-source voltage of S1 drops to zero, the parasitic diode of S1 turns on, clamping the drain-source voltage of S1 at zero voltage, thus creating conditions for zero voltage conduction of S1. At this time, the withstand voltage v1 on Lr is

v1=Vin＋NVo （5）

The current on Lr rises rapidly, while the current iD flowing through the secondary rectifier diode D drops rapidly.

diD/dt=－N[Vin+NVo]/Lr+NVo/Lm) (6)

Considering Lr?Lm, equation (6) can be simplified as

diD/dt=-N(Vin+NVo)/Lr (7)

8) Phase 8〔t7, t8〕At t7, the gate of S1 changes to high level, S1 turns on with zero voltage, and the current flowing through the parasitic diode flows through S1. At t8, the current of the secondary rectifier diode D drops to zero, D turns off naturally, and the circuit begins to enter the next cycle.

It can be seen that under this scheme, the two switches S1 and S2 are turned on at zero voltage, and the diode D is naturally turned off.

2 Parameter design of soft switch

Assume that the circuit works in CCM state. Since the soft switching of S2 is realized by Lr and Lm jointly charging Cr1 and Cr2, while the soft switching of S1 is realized by Lr alone charging and discharging Cr1 and Cr2. Therefore, the soft switching of S2 is easier to realize, while the soft switching of S1 is much more difficult. Therefore, in parameter design, the key is to consider the soft switching conditions of S1.

The design steps of the current continuous mode active clamped Flyback converter ZVS are described as follows.

2.1 Setting of transformer magnetizing inductance Lm

Due to the existence of Lr, the effective duty cycle Deff of the converter (defined according to the charging and discharging time of the excitation inductor Lm, see Figure 2) is smaller than the duty cycle D of S1. However, since the rising speed of iLr from t5 to t8 is very fast, it can be approximately considered that Deff = D. In this way, according to the Flyback circuit working in CCM conditions,

Where: η is the converter efficiency;

fs is the switching frequency;

PoCCM is the output power of the converter.

In actual design, in order to ensure that the circuit can work in the current continuous mode even when light load, Lm is generally taken as

2.2 Setting of inductance Lr

In order to achieve ZVS of S1, the energy stored in Lr at time t5 is sufficient to discharge the output junction capacitance Cr1 of S1 to zero, and charge the output junction capacitance Cr2 of S2 to the maximum. That is

, In the formula: vds=vds1=vds2≈Vin＋NVo;

Cr=Cr1+Cr2.

According to formula (4), the appropriate resonant period can be set to

2.3 Capacitor Cclamp setting

According to formula (4),

under the premise of satisfying formula (15), we can determine the appropriate Cclamp so that iLrmax=iLrmin.

2.4 Determination of dead time

In order to achieve ZVS of S1, it is necessary to ensure that S1 starts to conduct within the time from t6 to t7. Otherwise, the current on Lr will reverse and recharge Cr1, so that the ZVS condition of S1 will be lost. Therefore, the dead time setting after S2 is turned off and before S1 is turned on is crucial to the realization of ZVS of S1. The appropriate dead time is 1/4 of the resonant period of the inductor Lr and the output junction capacitance of S1 and S2, that is,

Strictly speaking, the output junction capacitance of the switching tube is a function of the voltage it is subjected to. For convenience, it is assumed here that Cr1 and Cr2 are constant.

2.5 Calculation of effective duty cycle Deff

The effective duty cycle Deff is slightly smaller than the duty cycle D of the switch tube S1.

Deff = D - ΔD (17)

[(Vin+NVo)/Lr]ΔDT≈2(P/DVin) (18)

ΔD≈2PLrfs/DVin(Vin+NVo) (19)

Substituting into formula (17) we get

Deff=D－2PLrfs/(DVin(Vin+NV0) (20)

2.6 Calculation of Switching Tube Voltage Stress

Vs1,s2≈Vin＋NVo＋(2PLrfs/DVin(1-D) (21)

The third term in equation (21) is relatively small, so the voltage stress of the switch tube is close to Vin + NVo.

3 Experimental results

In order to verify the above ZVS implementation method, an experimental circuit is designed, and its specifications and main parameters are as follows:

Input voltage Vin48V;

Output voltage Vo12V;

Output current Io0～5A;

Working frequency f100kHz;

Main switches S1 and S2 IRF640;

Transformer magnetizing inductance Lm 144μH;

The transformer primary-to-secondary turns ratio n=N8/3;

Inductor Lr 10μH;

Capacitor Cclamp 2μF.

Figure 4 shows the experimental waveform when the load current Io=2A. From Figure 4 (e) and Figure 4 (f), we can see that both S1 and S2 achieve ZVS. Figure 5 shows the efficiency curves of the two flyback circuits. It can be seen that the active embedded flyback soft switching circuit effectively improves the efficiency of the converter.

4 Conclusion

The active embedded Flyback soft switching circuit realizes the ZVS of the main switch and auxiliary switch, and also realizes the natural turn-off of the output rectifier diode, thus effectively reducing the switching loss and improving the converter efficiency. In addition, it also greatly reduces the voltage stress of the switch tube, which can be clearly seen from the experimental waveform.

Reference address：Active Clamp Flyback Soft Switching Circuit Design

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