1-wire system TM card single chip equivalent replacement

1 TM Card Introduction

TM (Touch Memory) card is a patented product of Dallas Company in the United States. It uses single-line protocol communication and completes data reading and writing through instant touch. It has the ease of operation of contactless IC cards and the cheapness of contact IC cards. It is one of the most cost-effective IC cards currently. Its appearance is similar to a button battery and can be embedded in cards, key chains and other objects.

The TM card uses a multifunction device to combine the data line, address line, control line and power line into one line to achieve single-line communication. When the host is powered on, the TM card responds to the host by switching between 500 kΩ and 50 Ω impedance, and uses the length of time (long or short) that the signal is pulled low to represent digital logic (long is 1, short is 0). Since the amplitude of the impedance switching is 10,000:1, the contact resistance of the contact will not affect the recognition of the digital signal.

2 1wire communication protocol

A single bus has only one data line, and data exchange and control in the system are all completed by this line. The device (host or slave) is connected to the data line through an open-drain or tri-state port to allow the device to release the bus when it is not sending data, allowing other devices to use the bus. A single bus usually requires an external pull-up resistor of about 4.7 kΩ, so that when the bus is idle, its state is high. The communication between the host and the slave can be completed in three steps: initializing the 1wire device; identifying the 1wire device; exchanging data. Since they are master-slave structures, the slave can only respond when the host calls the slave. Therefore, the host must strictly follow the single bus command sequence when accessing the 1wire device, that is, initialization, ROM command, and function command. If there is a sequence confusion, the 1wire device will not respond to the host (except for the search ROM command and the alarm search command).

SMC1990A1 is a 64-bit ROM ID code with factory laser marking, which includes a 48-bit serial number, an 8-bit CRC code and an 8-bit product series number. Data is transmitted in accordance with the single bus protocol, and the power for reading and writing is provided by the data line itself, without the need for external power supply.

3 Equivalent replacement of SMC1990A1

Single bus technology has the advantages of saving I/O port line resources, simple lines, low hardware expenses, low cost, and easy bus expansion and maintenance. It is widely used in distributed measurement and control systems. In actual application, TM cards may be lost or damaged. If this happens, it is often necessary to set the permissions of multiple acquisition points based on a new TM card. If there are many acquisition points, a lot of manpower will be wasted. At this time, it is necessary to use a single-chip microcomputer to replace the lost or damaged TM card.

3.1 System Hardware Composition

The system uses AT89C51 as the controller and a 24 MHz crystal oscillator. In order to adapt to the standard single bus communication protocol as much as possible, the crystal oscillator frequency should be as high as possible. Considering that all transmissions in the single bus communication protocol are initiated by the host, interrupt processing is used to respond to the host as quickly as possible. INT0 (i.e. P3.2) of AT89C51 is selected as the positive pole of the equivalent replacement of SMC1990A1. Figure 1 is a schematic diagram of the equivalent replacement of the TM card.

Figure 1 Equivalent replacement of TM card

3.2 System Software Design

The equivalent replacement of SMC1990A1 mainly focuses on the analysis of its timing. For SMC1990A1 sub-device, the main programming is for the host, and the transmission is initiated by the host. Now it is changed to a single-chip microcomputer to simulate the SMC1990A1 sub-device (now called "slave").

Figure 2 Initialization sequence

First, the initialization sequence is shown in Figure 2. The host first sends a reset pulse, which lasts for tRETL (a low-level signal with a minimum duration of 480 μs), then releases the bus and enters the receiving state. After the slave detects the rising edge of the bus, it waits for tPDH time, pulls the bus low to send a presence pulse, which lasts for tPDL (low level, lasting 60 to 240 μs), and then releases the bus. Releasing the bus is achieved by pulling the bus high.

Corresponding to the slave, the interrupt service program flow of the initialization sequence is shown in Figure 3.

Figure 3 Interrupt service program flow of initialization sequence

The following is the master write 0 and write 1 timing. After the initialization timing, when the host bus is pulled from high level to low level, a write time gap is generated. Within the first 15 μs, the bit to be written should be sent to the bus, and the slave will sample the bus between 15 and 60 μs after the start. If it is low level, the written bit is 0, as shown in Figure 4; if it is high level, the written bit is 1, as shown in Figure 5. The gap tREC between consecutive writes of multiple bits should be greater than 1 μs.

Figure 4 Host write 0 timing

Figure 5 Host write 1 timing

Corresponding to the slave, it is waiting for the host command. The interrupt service program flow of the slave waiting for the host command is shown in Figure 6.

Figure 6 The interrupt service program flow of the slave waiting for the host command

Finally, the host reads data timing, as shown in Figure 7. When the host bus is pulled from high level to low level at the beginning, the bus only needs to maintain low level for 1 to 7 μs. After that, the bus is released at tLOWR, and the bus is generally sampled at tRDV (15 μs). The read time gap is valid between tLOWR and tRDV. The slave must pull the bus high or low before tRDV, and the host samples at tRDV and releases the bus within 60 to 120 μs.

Figure 7 Host read data timing

For the slave, it is a 64-bit ID process. The difficulty of program processing is that the slave must pull up or pull down the bus before 15 μs so that the host can sample the bus at 15 μs. The program implements this function by judging the state at bit address 00H. The state at bit address 01H is used to determine whether to send bit 0 or send bit 1. The interrupt service program flow of the slave sending 64-bit ID processing is shown in Figure 8.

Figure 8 Interrupt service routine flow for slave sending 64-bit ID processing

In the process of completely implementing a ROM function, the slave first waits for the reset pulse sent by the host, and then sends a pulse response after detection. Subsequently, the slave starts to receive the ROM command sent by the host and saves it to determine the subsequent operation. Finally, the slave sends the 64-bit identification code of the TM card to complete the execution of a ROM command. The process of implementing the ROM function is shown in Figure 9.

The assembly program of the microcontroller is as follows:

ORG0000H
AJMPInit//Jump to Init segment
ORG0003H
AJMPJudge//Jump to interrupt service routine
Init: //Initialization
MOVDPTR,#ID//ID table address
MOVR5,#001H
MOVR7,#000H
CLR00H
SETB01H
SETBP3.2
LCALLDelay10s
CLRP3.2//Pull down the bus to wake up the host
LCALLDelay100us
SETBP3.2
SETBEA
SETBIT0
SETBEX0
MAIN: AJMPMAIN//Main loop
Judge:CLREX0//Judge the execution action, turn off interrupt
JNB00H,SecondJ//Jump to secondary judgment
ID_IN:JB01H,SEND1//Slave sends TM card 64-bit identification code
CLRP3.2//Send bit 0
SEND1:SETBP3.2 //Send bit 1
LCALLDelay30us
MOVA,R5 //R5 circularly shifts left
RLA
MOVR5,A
MOVA,#00H
MOVCA,@A+DPTR
ANLA,R5
CLR01H //Set 01H status
JZRelease1
SETB01H
Release1:SETBP3.2
MOVA,R5
ANLA,#080H //Judge whether the byte has been sent
JZINTEND
INCDPTR
AJMPINTEND //Jump to the end of the interrupt
Second J:MOVA,R7 //Second judgment
JZWaitReply //Jump to execute the response to determine whether the command reception is completed
ANLA,#008H
JZWaitOrder //Jump to execute the receiving command
SETB00H
WaitOrder: LCALLDelay15us //Receive command
NOP
NOP
MOVA,P3 //Sampling P3.2
ANLA,#004H
JZSAVE_R6
MOVA,#001H
SAVE_R6:
ORLA,R6 //Save command to R6
RRA
MOVR6,A
RLOOP1:
MOVA,P3 //Judge the host's sending status, whether to return
ANLA,#004H
JZRLOOP1
AJMPINTEND //Jump to the end of interrupt
WaitReply://Execute reply
RLOOP:MOVA,P3 //Judge the host's reset signal
ANLA,#004H
JZRLOOP
LCALLDelay30us
CLRP3.2 //Slave pulls low level to respond
LCALLDelay150us
SETBP3.2 //Release bus
NOP
NOP
NOP
NOP
INTEND:
INCR7
CLRIE0
SETBEX0 //Open interrupt
RETI //Interrupt return
ID:DB001H //ID table
DB0C3H
DB04DH
DB057H
DB033H
DB022H
DB000H
DB0D2H

The code in this article has been well verified in practical application and can stably replace SMC1990A1 to implement the ROM function of the TM card, which greatly facilitates the permission management personnel to manage the lost or damaged TM cards.