Reset Problems in MCS-51 Interrupt System

The MCS-51 series of microcontrollers provide multiple interrupt sources (8051 provides 5, 8052 provides 6 interrupt sources). Each interrupt source can be programmed with two levels of interrupts, high-level interrupt requests and low-level interrupt requests, so two-level interrupt service nesting can be achieved. Even for interrupt sources of the same level, when requesting interrupts at the same time, the CPU response has a different order. Therefore, MCS-51 is widely used in real-time systems and instrumentation. The design of the interrupt system is a key point in software design. If it is not handled properly, the software will often fail to achieve the designed effect.

The following is a problem I encountered during the application process.

The power meter we designed contains a keyboard and a second clock. The keyboard interrupt uses INT0, and the second clock uses T0. INT0 is set as a high priority interrupt, and T0 is a low priority. The second interrupt service takes about 750ms. The CPU is required to have a high response speed to the keyboard, and once a valid keyboard command is received, the program will re-enter the measurement state from the waiting position and will not return to the place where it was interrupted by the keyboard. The software flow is shown in Figure 1.

The original keyboard service program ends as follows:

During the debugging process, after responding to the keyboard interrupt, it is often unable to enter the second interrupt normally, and only waits in the WAIT loop. At this time, EA=1, TR0=1, TF0=1. It can be seen that EA=1, TR0=1, TF0=1 are not sufficient and necessary conditions for interrupt T0 response.

After consulting relevant information from multiple sources, it was discovered that the interrupt system of the MCS-51 series microcontrollers has two non-addressable priority status triggers. Their set states, one indicates that the CPU is executing a high-priority interrupt service program, and the other indicates that a low-priority interrupt service is being executed. The set states of these two triggers respectively shield all interrupt requests and other interrupt requests of the same priority level.

The second interrupt service takes 750ms. When the keyboard is pressed, there is a 75% chance that the second interrupt service program is being executed, indicating that the trigger for executing the low-priority interrupt service has been set. After responding to the keyboard interrupt, the trigger for executing the high-priority interrupt service is set. However, only one RETI instruction is executed during the entire process, indicating that the trigger for the CPU executing the T0 interrupt is not reset. Even if TR0=1, TF=1, and EA=1, the CPU still believes that the program has executed the second interrupt service, and therefore cannot enter the second interrupt service again. For this reason, the author changed the original program to

After the assembly is loaded into the system, everything is normal.