FPGA parallel configuration method based on microcontroller

In today's changing market environment, whether a product is easy to upgrade on site and easy to use flexibly has become a key factor in whether a product can enter the market. In this context, Altera's FPGA devices based on SRAM LUT structures have been widely used. Configuration data for such devices is stored in SRAM. Due to the volatility of SRAM when power is lost, the data must be reconfigured every time the system is powered on. The system can only operate normally if the data configuration is correct. The advantage of this device is that it can be reconfigured online (In-Circuit Reconfigurability). There are generally two types of online configuration methods: one is to configure it directly by the computer by downloading the electricity bill; the other is to configure it through a microprocessor. The former is very convenient during debugging, but it is very unrealistic at the application site. Therefore, if the system itself has the ability to automatically load the programming file of the programmable logic device when the system is powered on again to complete the configuration of the programmable logic device, the process of manually configuring the device by downloading the electricity bill can be omitted. This automatic loading configuration is necessary for some applications of FPGA. In an interference system that the author participated in the development of, the microcontroller AT89C52 was used to perform online parallel configuration of the EPF10K10 in the FLEX10K series FPGA, and achieved good results.

1 Configuration methods and configuration files of FPGA devices

1.1 Configuration method of FPGA device

FPGA devices with ICR functions produced by ALTERA include FLEX6000, FLEX10K, APEX and ACEX series. Their configuration methods can be divided into five methods: PS (Passive Serial), PPS (Passive Parallel Synchronization), PPA (Passive Parallel Asynchronous), PSA (Passive Serial Asynchronous) and JTAG (Joint Test Action Group). These five methods are suitable for microcontroller configuration. The PS method is widely used because of its simple circuit and relatively low requirements for configuration clocks. In contrast, solutions using PPA configuration are rarely seen. However, since the PPA configuration mode is parallel configuration, its configuration speed is fast, and the configuration clock is generated internally by the FPGA (while configuration modes such as PS require an external configuration clock), it is more conducive to online implementation. The configuration solution in this article is implemented using PPA configuration.

Figure 1

　　 1.2 Configuration file of FPGA device

ALTERA's MAX+PLUS II development tool can generate a variety of configuration or compilation files for configuration systems with different configuration methods. For different target devices, the size of the configuration data is different, and the size of the configuration file is generally determined by the .tbf file (ie, binary file). In this example, the size of the configuration file .rbf of EPF10K10 is 15k. This file includes all configuration data. A one-byte .rbf file has 8 bits of configuration data. Since the software tools provided by Altera do not automatically generate .rbf files, the files need to be generated according to the following steps: ① In the MAX+PLUS II compilation state, select the Convert SRAM Object File command in the File menu; ② In the Convert SRAM Object File dialog box, specify the file to be converted and select the output file format as .rbf (Sequential), then confirm.

2 Hardware circuit design

The hardware circuit diagram of the parallel configuration of AT89C52 to EPF10K10 is shown in Figure 1. The configuration file (.sof) is generated by MAX+PLUS II compilation, converted into a (.rbf) file through format and stored in the memory shown in the figure. When using the PPA configuration method, MSEL1 and MSEL0 need to be set to high level. In order to prevent DCLK from having an uncertain signal, it must be pulled up to Vcc through a 1kΩ resistor. When using the PPA configuration method, only one of the two chip select signals nCS and CS is used. Therefore, if one of them is used as the chip select signal, the other must be directly set to the valid position; if CS is selected as the chip select signal control configuration, nCS must be connected to ground; if nCS is selected as the chip select signal control configuration, CS must be connected to high level . The latter is used in this example. NRS is the read strobe input signal. When it is a low input, FLEX10K places the RDYnBSY signal on the DATA7 pin. When nRS is not used, it must be set high. nCE is the enable input of the FLEX10K device, and the configuration process is enabled when nCE is low. When the device is in a monolithic configuration, nCE must always be low. Since this example is a monolithic configuration, connect nCE directly to ground. Then connect the nCONFIG, CONF_DONE, nSTATUS, and RDYnBSY of EPF10K10 to the P17, P14, and P13 pins of AT89C52 respectively. DATA[7..0] is connected to P07~P00 of AT89C52. NWs is the write strobe input, which latches the byte data on the DATA[7..0] pin when it transitions from low to high. It should be noted that the nSTATUS pin and CONF_DONE pin are bidirectional open-drain outputs. When used as outputs, they should be pulled up to Vcc through a 1.0kΩ resistor.

Figure 2

3 Software design

3.1 Configuration principle

The download timing of PPA configuration mode is shown in Figure 2. It can be seen from the figure that the working process of PPA mode is as follows:

(1) Startup configuration

Generate a low pulse on the nCONFIG pin and wait for nSTATUS to respond with a low pulse and CONF_DONE to go low. 4μs after nCONFIG jumps high, internal nSTATUS also jumps high, indicating that the FPGA can be configured.

(2) Configuration process

When configuring the FPGA, the microcontroller places the 8-bit configuration data on the data end of the FPGA device and gives nWS a negative pulse. On the rising edge of nWS, the FPGA device latches the byte configuration data; then the FPGA device drives RDYnBSY is low, indicating that it is processing this byte of information, and the configuration process can be paused through the nCS and CS pins. When RDYnBSY is low, the FLEX10K device uses its internal oscillator (its frequency is generally 10MHz) to serialize each byte of configuration data internally. When the FLEX10K device is ready to receive the next configuration data, it drives RDnBSY high. After the microcontroller detects the high-level signal, it sends the next byte of data. This process continues until all data configuration is completed. During the configuration process, the system needs to perform real-time monitoring. Once an error occurs, nSATUS will be pulled low. The system must be able to recognize this signal and restart the configuration process.

Figure 3 (3) End configuration

　　 

After all the configuration data is correctly written into the chip, the device releases CONF_DONE and pulls it high externally. If the microcontroller detects this signal, it indicates that the configuration is successful; otherwise, it needs to be reconfigured.

3.2 Configure soft design

The control program flow chart of the single-chip microcomputer implementation of the configuration process is shown in Figure 3.

The assembly programming program is designed as follows:

nCONFIGEQU P1.7

nSTATUS EQU P1.5

RDYnBSY EQU P1.3

CONF_DONE EQU P1.4

ORG 0000H

LJMP MAIN

ORG 0030H

; Initialize the data length related, where the data length to be configured is placed at addresses 0000H and 0001H

;0000H puts the low bit of the data length, 0001H puts the high bit of the data length

; Starting from 0002, the data to be configured is placed.

MAIN: MOV DPTR, #0000H

MOVX A, @DPTR

MOV R3,A; R3 places the low bit of the configuration data number

MOV DPTR, #0001H

MOVX A, @DPTR

MOV R4,A; R4 places the high bit of the configuration data number

MOV R5, #00H; put the low bit of the configuration data number

MOV R6, #00H; put the high bit of the configuration data number

;The following is a subroutine for configuring data

COFIG: MOV DPTR, #0002H

CLR P1.7

ACALL DELAY4; delay is about 15μs

JB nSTATUS,COFIG; Check whether the FPGA responds and sets the low bit

SETB nCONFIG; After FPGA responds to setting low, set nCONFIG to high

STA_JUDGE:JB nSTATUS,COFIG_BEG; wait for the FPGA to respond and set the high bit, and then prepare to configure

LJMP STA_JUDGE

COFIG_BEG:ACALL DELAY2

LJMP SEND_DATA

READY_DATA1:JNB nSTATUS,COFIG

SEND_DATA:MOVX A,@DPTR; read data

PUSH DPH

PUSH DPL

MOV DPTR, #7000H; read in FPGA address

JNB P1.3,$; Determine the status of RDYnBSY

MOVX @DPTR,A; configuration data

POP DPL

POP DPH

INC DPTR

;The following implements the judgment of configuration

CLR C;

MOV A, #01H

ADD A,R5

MOV R5,A

MOV A, #00H

ADDC A, R6

MOV R6, A

MOV A, R5

CJNE A,03H,RESESH_COFIG

MOV A,R6

CJNE A,04H,RESESH_COFIG

CON_REFRESH:ACALL DELAY2; Delay 5μs, JB P1.4, END1; Determine the status of CONF_DONE to see if the configuration is successful

LJMP COFIG

PESESH_COFIG:LJMPREADY_DATA1

;Delay subroutine, delay is about 5μs

DELAY2：NOP

NOP

NOP

NOP

NOP

RET

;Delay subroutine, delay is about 15μs

DELAY4: MOV R1, #08H

DJNZ R1, $

RET

END1:END

The FPGA parallel configuration method based on microcontroller discussed in this article has the characteristics of simple circuit structure, easy development and low cost. Compared with the commonly used serial configuration method, this configuration method has the advantages of short configuration time, high accuracy, and easy implementation. Although this configuration control circuit is designed for configuring ALTERA's FLEX10k series FPGA devices, it can also be applied to other series of FPGA devices with slight modifications, so it has certain versatility.