DVB-C Set-Top Box Source Decoder Based on SC2005

In the development process of set-top boxes, the development of source decoders is the foundation and core of the entire development work. With the introduction of the machine-card separation policy, the versatility and complexity of source decoders make them more important in the development process of set-top box terminals. This article discusses the design and implementation of a source decoder for digital cable TV set-top boxes that complies with the DVB-C standard.

Overall plan

The set-top box can be roughly divided into two functional parts: the channel demodulation and decoding part and the source decoding part. The channel part is the front end, which is responsible for demodulating, receiving and channel decoding of digital TV signals. Due to the difference in the front end, the set-top box can be divided into three types: digital satellite set-top box, digital terrestrial set-top box and digital cable set-top box.

The source decoder is developed for digital cable TV set-top boxes. It will be equipped with the L64768 front end to form a complete set-top box solution that complies with the DVB-C standard. This article uses LSI Logic's second-generation single-chip source decoding solution based on SC2005 to implement the decoding function. The structural block diagram of the decoder is shown in Figure 1. It can be divided into four parts according to function: the CPU and storage control subsystem with SC2005 as the core; the transport stream demultiplexing and audio and video decoding subsystem; the graphics processing and screen menu display and output subsystem; and the peripheral interface subsystem.

Figure 1 Set-top box source decoder

Hardware Implementation

The startup code of the source decoder is stored in the Flash Boot ROM, and the fonts used are stored in the Flash Font ROM. The two SDRAM memory interfaces of SC2005 are connected to SDRAM-A and SDRAM-B respectively. After the system is powered on, the startup code stored in the Flash Boot ROM is transferred to SDRAM-B for execution. The clock is provided by a 27MHz voltage-controlled oscillator after frequency multiplication. The clock signal generated by the voltage-controlled oscillator is shaped by 74LVC14 and sent to the VCXO pin of SC2005, and synchronized and restored through the output of the SDET pin. The functions of transport stream multiplexing, audio and video decoding, and graphics processing are all realized by the corresponding integrated modules inside SC2005 in conjunction with external related circuits.

CPU and storage control subsystem

SC2005 integrates the functions of transport demultiplexer L641x8 and MPEG-2 audio and video decoder L64105, and contains EZ4102 core, 16KB instruction cache and 8KB data cache, which are the core components of SC2005.

The two 1M×16bit Flash ROMs used in the source decoder are both AM29LV160DT-70, powered by a single power supply, using 3.3V voltage for reading, writing and programming, and high-speed 70ns reading and writing time. They are connected to SC2005 through E-Bus, the address bus A[6:0] is connected to SC2005's ADDR[7:1], A[19:7] is connected to SC2005's AD[28:16], and the data bus DQ[15:0] is connected to SC2005's AD[15:0]. There are 35 sectors in the chip, 4 of which are used as boot sectors with a size of 4k words and 16k words, and the remaining 31 sectors are 32k words; there is a byte/word mode selection pin BYTE#, which is connected to a high level in this design to select word mode.

The 81MHz/1M×16bit SDRAM-A and 108MHz/2M×16bit SDRAM-B are connected to the CPU's SDRAM memory interface via S-BUS. SDRAM-A is used to store video frames and related information during MPEG decoding, while SDRAM-B stores information for demultiplexing, OSG, and peripheral device interface subsystems. Data can be directly transferred between SDRAM-A and SDRAM-B via a DMA engine.

Transport stream demultiplexing and audio and video decoding subsystem

SC2005 first receives the TS stream from the channel decoder or code stream generator, and then automatically performs transmission packet synchronization detection. Once synchronization is established, the transmission packet will be sent to the PID preprocessor. The PID preprocessor analyzes the input transmission packets and checks their PID values. Only the PID values ​​that match the PID table can pass the first step of filtering, and the unmatched packets are discarded. The transmission packets that pass the PID filter are sent to the DVB descrambler, and the descrambled packets enter the PID postprocessor. After filtering, the audio and video PES data directly enters the A/V decoder, while other data is sent to the external SDRAM-B circular buffer. The CPU can read data directly from the memory. The structural block diagram of the transport stream demultiplexing subsystem is shown in Figure 2.

Figure 2 Transport stream demultiplexing subsystem

The demultiplexed audio and video PES stream enters the L64105 MPEG-2 decoder through the A/V interface for packet decoding. The L64105 outputs two groups of digital video and digital audio signals. One group of digital video and one group of digital audio signals are directly output. The other group of digital video signals is sent to the video encoder and converted into a full TV signal (CVBS) or S-terminal signal (Y/C), and is directly sent to the TV after external low-pass filtering; the digital audio signal is sent to the audio DAC, converted into a stereo analog signal, and output after external low-pass filtering.

Graphics and on-screen menus

Display Output Subsystem

SC2005 integrates a high-performance OSG (On-Screen Graphics) subsystem, which can generate text and graphics and overlay them on the decoded video. The OSG subsystem generates the static layer, OSD layer and cursor layer; the decoding subsystem provides the video layer; the mixer/encoder subsystem generates the background color layer and encodes and composites the above 5 layers before the video is output, so as to display the composite video to be output as needed. This subsystem mixes and encodes the graphics and decoded video data from the OSG subsystem, and then outputs NTSC/PAL/SECAM RGB/YPbPr, CVBS or S video signals to the TV or monitor.

Figure 3 ATA hard disk interface

Peripheral Interface Subsystem

The source decoder integrates an ATA hard disk interface, as shown in Figure 3. Users can use this interface to realize the function of a personal video recorder (PVR); they can also open a massive cache area in the hard disk to store programs for several hours in real time while playing digital TV. Relying on this cache technology, users can perform time-shift playback.

The decoder has a TDA8004T smart card interface and a JTAG module that complies with the IEEE 1149.1 standard, providing basic debugging functions. It also provides an LVDS interface to receive the TS stream output by the code stream generator. The LVDS signal input from the DB-25 interface is converted by three DS90C032 chips before entering the decoder. In addition, the system also uses a UART for set-top box debugging and software upgrades.

Software Design

The software system is based on a layered framework, some of which are provided by LSI Logic in its reference software, and other parts need to be developed by the user. The overall structure of the software is shown in Figure 4.

The real-time operating system layer (RTOS) is the basis for the operation of all upper-level program codes, and is mainly responsible for multi-task scheduling, system resource management, interrupt processing, communication operations and synchronization processing. This article uses a modular, high-performance real-time operating system pSOSystem designed and developed by WindRiver for embedded systems. The RTOS layer uses a board support package (BSP)

To implement the interface with the hardware layer.

The operating system porting layer (OSP) implements two main functions: one is to dynamically configure the attributes of tasks, such as context switching, priority, etc.; the other is to manage the communication between tasks, such as data transmission and synchronization. The hardware abstraction layer (HAL) is responsible for programming the hardware registers directly; the device driver layer (DDL) is a clear and convenient backup and encapsulation of the hardware abstraction layer, mainly providing corresponding drivers for each hardware module, such as the driver for SC2005 exception handling, the driver for the clock service module, and the driver for the OSG graphics library. The application interface layer (API) provides API functions for upper-level applications.

The driver adaptation layer (DAL) is a further collection of device driver layer functions. Through the combination of functions, it can be directly applied to the application layer, and it plays the role of an interface. For example, for Flash operations, such a driver adaptation layer can be used to further encapsulate the functions to facilitate the call of the upper application.

The user application layer is the main part of the set-top box user application software and the focus of software development. All upper-layer functions related to the set-top box are implemented in this layer, such as the implementation of user interface functions, EPG implementation, program database management, user information input/output control and software upgrades.

Performance Test Results

After the source decoder is connected to the L64768 front end, it has been tested and has achieved the expected functions. Its performance characteristics are as follows:

1. The whole system fully complies with DVB-C/MPEG-2 standards

2. Channel decoding supports 16/32/64/128/256QAM, conversion rate: 3MSPS" 7MSPS

3. TS demultiplexer maximum input bit rate: 60Mbps (serial 1)/7.5Mbps (parallel)

4. Video decoding resolution: Max720×576, support graphics and subtitles

5. Audio decoder sampling rate: 32/44.1/48kHz, support 32-level volume adjustment

6.Support ATA hard disk interface

Conclusion

This paper implements a DVB-C set-top box source decoder based on SC2005, integrates a personal digital video recorder, and connects it to the L64768 front end to form a functional prototype that meets the standards.