FreeRTOS porting on GD32VF103 processor![Copy link]
RISC-V is an open source instruction set architecture (ISA) based on the principle of reduced instruction set computing (RISC) and has a wide range of application prospects. This article will use GigaDevice's GD32VF103V-EVAL development board and IAR EWRISC-V toolchain to introduce how to port FreeRTOS to GD32VF103 and use Percepio's Tracealyzer tool to verify the porting results.
GD32VF103 RISC-V MCU
GD32VF103VBT6 uses Nuclei's Bumblebee kernel and supports the RV32IMAC instruction set; it supports machine mode and user mode to improve software security. The register group contains 32 general registers, RISC-V standard status registers and kernel-defined CSR registers. The kernel provides a timer unit (TIMER), and the timer interrupts and software interrupts generated can be used for RTOS clock beat processing and task switching.
The Bumblebee kernel provides an "Enhanced Core Local Interrupt Controller (ECLIC)" optimized based on RISC-V CLIC to manage all interrupt sources. Each interrupt source of ECLC can be configured as vector or non-vector processing mode.
FreeRTOS and Tracealyzer
Amazon FreeRTOS is a widely used RTOS under the MIT license. FreeRTOS provides standard RISC-V kernel porting examples for IAR and GCC toolchains, supporting 32-bit and 64-bit architecture kernels. FreeRTOS supports two task scheduling methods: preemption and time slice polling, and supports an unlimited number of application tasks.
The Tracealyzer tool runs on a Windows or Linux PC and can be used to analyze the RTOS behavior of the target system. It can quickly and easily collect useful and meaningful behaviors of multi-tasking software. It can be quickly integrated into the existing development environment to collect system runtime data in snapshot mode or streaming mode. It provides more than 30 views to visualize the RTOS runtime behavior, helping developers solve problems, improve software reliability, and improve software performance.
FreeRTOS ported to GD32VF103
Most of the FreeRTOS kernel is written in C language, and only the context switch related to the processor is implemented in assembly language to ensure the efficiency of context switching. The key points of the porting are to achieve:
1. How to turn interrupts on and off;
2. How to enter and exit the critical region;
3. Generate periodic interrupts as the system clock beat;
4. Task context switching;
Interrupt management and critical section implementation
The ECLIC interrupt controller of GD32VF103 has an interrupt target threshold level register (mth). Interrupts with a priority level lower than this threshold will not be responded to. When porting FreeRTOS, the switch interrupt is implemented by setting mth. Interrupts with a priority level higher than the threshold are not managed by FreeRTOS, and there is no additional delay for the interrupt.
The critical section of the code is also called the critical segment of the code. This part of the code is not allowed to be interrupted during execution. The critical section of FreeRTOS is implemented by disabling interrupts. Interrupts must be disabled before entering the critical section, and interrupts must be enabled immediately after the critical section code is executed.
System clock tick
Operating systems require a clock tick to implement time-related processing such as system delay and timeout. The clock tick is a specific periodic interrupt, and the interrupt period is the tick duration. The length of the tick is determined by the actual application. The higher the frequency of the clock tick, the greater the system overhead.
The RISC-V architecture defines a 64-bit width mtime counter. When the mtime count value increases to the value preset by the mtimecmp register, an interrupt can be generated. The mtime counter is selected to generate the system clock beat. The value of mtimecmp is calculated based on the clock frequency of mtime and the system beat frequency. When an interrupt occurs, the interrupt is cleared by rewriting the value of mtimecmp or mtime. Therefore, mtime is used to generate the clock beat required by FreeRTOS.
Implementing context switching
Context is the register content of the CPU at a certain point in time. The key to FreeRTOS's correct task scheduling is context switching. The process of context switching includes: saving the running scene of the task that is about to exit the running state to its task stack; restoring its running scene from the stack of the next task to be run. The context switching time should be as short as possible, so it is generally written in assembly code as part of the operating system porting.
Task scheduling may be performed in the ISR. In order to be able to perform context switching after the ISR exits, the code to implement context switching is generally placed in the exception handler, and the priority of the exception is set to the lowest. After the task scheduling is completed, the exception of switching context is triggered, and the exception service program begins to execute after all interrupts with higher priority levels exit.
There are two types of exceptions that can be used for task switching on RISC-V processors: ecall exceptions and software interrupts. The ecall exception is triggered by calling the ecall instruction; the software interrupt is triggered by writing "1" to the msip register and cleared by writing "0". The software interrupt of GD32VF103 is connected to the ECLIC unit for unified management. This FreeRTOS porting uses software interrupts as the implementation mechanism for context switching. eclic_msip_handler() is the ISR of the soft interrupt, and the context switching is placed in this ISR.
3.1 Migration file modification
The FreeRTOS processor-related code exists in the three files port.c, portASM.s and portmacro.h as part of the porting. The portmacro.h header file defines the data types used by FreeRTOS, macros for entering and exiting critical sections, macros for implementing switch interrupts, and macros for triggering and clearing software interrupts.
The vPortStartFirstTask() function is implemented in assembly in portASM.s to start the first task. Its core operation is to take out the stack pointer SP of the highest priority task among the currently ready tasks from pxCurrentTCB and restore the register scene through SP.
Implement the software interrupt service function eclic_msip_handler(), save the current register context (general registers x1, x5~x31; machine mode status register mstatus; machine mode exception PC register mepc) to the stack of the currently running task, then take out the stack pointer SP of the next ready task with the highest priority from pxCurrentTCB to restore the register context and complete the task context switch.
The port.c file focuses on implementing the stack initialization function pxPortInitialiseStack(), the specific processing function xPortStartScheduler() when starting the FreeRTOS scheduler, the system clock tick timer initialization function vPortSetupTimerInterrupt(), and the system clock tick interrupt service function xPortSysTickHandler(). These functions need to be implemented according to the RISC-V architecture and the hardware characteristics of the GD32VF103 microcontroller.
3.2 Transplantation Testing and Verification
Verify that the transplantation is fully functional by debugging and using the corresponding auxiliary tools. Use IAR EWRISC-V to create a project and create two or more tasks in the code for debugging. When debugging the code, you need to verify:
1. By adding breakpoints in the system clock beat ISR and software interrupt ISR, combined with the RISC-V mtime and mcycle registers, verify that the system clock beat is generated correctly and the software interrupt can be triggered normally.
2. When starting the first task, add breakpoints to check whether the register contents restored from the task stack are consistent with the contents written when the stack was initialized, so as to test the correctness of the pxPortInitialiseStack() and vPortStartFirstTask() functions.
3. When executing task context switching, add breakpoints in the software interrupt service routine, execute it step by step, and use the EWRISC-V memory observation window to check whether the content pushed into the current task stack is the same as the corresponding register content; when restoring the following content, check whether the register content restored from the next execution task stack is consistent with the stack. Verify the correctness of the context switching of the eclic_msip_handler() software interrupt service function.
4. Start the first task and verify the code of task context switching to work properly. The transplanted FreeRTOS can realize basic task scheduling. Then continue to test whether the switch interrupt operation and critical section are normal. To test the switch interrupt, you need to add another peripheral interrupt, set its priority level to be greater than or less than the mth threshold for testing. Manually call the switch interrupt operation API in the code to detect whether the interrupt trigger is in the designed mode, and verify FreeRTOS's control of interrupts. The same method is used to test entering and exiting the critical section.
5. Through the FreeRTOS system service call test, test whether the system services, such as semaphores, message queues, event flags, etc., are normal. And test whether the operations such as sending signals and messages in the ISR managed by FreeRTOS are also correct.
After the basic debugging tests are passed, it is possible to verify whether the porting is successful. On this basis, you can also use additional tools to continue verification, such as the FreeRTOS debugging plug-in that comes with EWRISC-V to confirm the information displayed.
Tracealyzer's trace recorder library is a software library that runs on the embedded target side and is integrated with the FreeRTOS project. It is responsible for recording the events generated by the RTOS during runtime. If the recorded events are stored in the event cache located in RAM, this working mode is called snapshot mode. If they are sent to the PC software in real time through the communication port, they work in streaming mode. The trace recorder library has no dependency on the processor hardware. It only needs to use a high-precision timer to generate timestamps to add time information to the recorded events.
RISC-V processors can use the core's mcycle counter to generate timestamps. mcycle is a 64-bit counter that counts CPU cycles, so the frequency is the same as the CPU clock and the accuracy is very high. mcycle consists of two 32-bit registers, and Tracealyzer only needs to use the lower 32-bit register.
Tracing and profiling FreeRTOS
Add the Tracealyzer trace recorder library to the FreeRTOS project of EWRISC-V, and make necessary configurations to work in snapshot mode. Create four tasks in the application code, namely Led1Task~Led3Task, ButtonTask, with increasing task priorities. Run the program for a while, save the snapshot data into a Hex file through EWRISCV and load it into the Tracealyzer on the PC for analysis.
View the execution status of each task through the horizontal timeline view: each task or interrupt occupies a row, and the timeline direction is from left to right. The colored rectangle in the row is an execution instance of the task or interrupt. The timeline window can quickly preview the execution status of the system during the entire operation process. After enlarging the time resolution of the window, you can carefully understand the relevant kernel events and time information when the task is executed.
Through the traced events and recorded timestamp information, Tracealyzer can generate multiple views to observe problems existing in the system runtime, such as thread starvation and deadlock caused by design defects, and find unnecessary delays in the system, helping developers solve system problems and improve the real-time performance of embedded systems. These problems are difficult to find using traditional debugging methods, and they are inefficient.
This paper introduces the method and process of porting FreeRTOS on the IAR EWRISCV tool chain based on the RISC-V instruction set microcontroller GD32VF103, as well as the method of verifying the ported system. On this basis, the Tracealyzer trace recorder library is ported, and the operation of the system is further observed by tracing the operation of the FreeRTOS system, and the execution of the task is analyzed.
Compared with the official introductory manual of FreeRTOS, I feel that the original poster's post contains a lot of valuable information.
I still don't quite understand it at the moment, I will continue to learn. Thanks for sharing!
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Published on 2022-12-1 01:03
Transplant freertos and realize multi-tasking operation. It is a very good test. I look forward to more exciting works in the future. If possible, attach your successful DEMO file so that later friends can quickly master it.
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