Application of synchronous queue serial interface QSPI

1 QSPI Working Principle

The structure of the QSPI module is shown in Figure 1. Compared with SPI, the biggest feature of the QSPI structure is that the SPI transmit and receive data registers are replaced by 80 bytes of RAM. The 80 bytes of RAM are divided into 3 parts: 16 words of transmit RAM, 16 words of receive RAM and 16 bytes of command RAM. These 3 parts form a transmission queue with 16 QSPI transmission control groups . Each QSPI transmission control group consists of 1 command RAM, 1 transmit RAM and 1 receive RAM. The data length, chip select and other information of each QSPI transmission can be determined separately by the command RAM of the QSPI transmission control group.

Since SPl has only one 8-bit transmit data register, the CPU can only prepare one byte of data to be transmitted at a time. QSPI has a transmission queue with 16 QSPI transmission control groups, so the CPU can prepare up to 16 data to be transmitted at a time, and can set the length of each data to be transmitted through the command RAM.

In the QWR register of the QSPI module, the NEWQP and ENDQP fields determine the start and end points of the transmission queue respectively. The start and end points can be 16 QSPI

Any one of the transmission control groups. When the QSPI transmission starts, the QSPI module will send the prepared data sequentially from the starting point to the end point, and the whole process does not require CPU intervention. The typical QSPI transmission process is shown in Figure 2, where QP is the transmission queue pointer, pointing to the data to be transmitted.

The QSPI module has 7 pins: QSPI_DIN is the serial data input pin; QSPI_DOUT is the serial data output pin; QSPI_CLK is the serial clock output; QSPI_CS[3:0] is the chip select signal, and up to 16 devices can be selected through an external decoder. A typical 16-bit QSPI transmission timing is shown in Figure 3. This timing assumes that the chip select signal is valid at a low level, the clock is at a low level when idle, and the serial data is sampled on the falling edge of the clock. Among them, the clock idle level and the sampling clock edge are determined by the CPOL and CPHA fields of the QMR register.

2 Introduction to 4-wire resistive touch screen chip ADS7843

ADS7843 is a 4-wire resistive touch screen control chip with synchronous serial interface and 12-bit analog/digital conversion accuracy. The 4 analog voltage input pins X+, X-, Y+, and Y- of ADS7843 are connected to the 4 electrodes of the touch screen. The touch screen sends the contact voltage to ADS7843 through these 4 pins for quantization. Specifically, if you want to obtain the Y coordinate of the touch point, ADS7843 will apply a voltage between Y+ and Y-, and the contact will conduct X+ with a point of the resistor network between Y+ and Y-. The voltage divider value related to the contact position will be sent to ADS7843 through X+, and the Y coordinate of the touch point can be obtained by quantizing this voltage divider value. The same principle applies to the acquisition of the X coordinate. The quantization step is determined by the reference voltage and the number of bits n after each sample point is quantized, which is 1/2 of the reference voltage.

2.1 ADS7843 Operating Mode

ADS7843 has two working modes: single-ended mode and differential mode. The difference between the two modes is that the reference voltage is constructed in different ways. The reference voltage is the difference between the positive and negative reference voltages +REF and -REF of the A/D conversion module inside the ADS7843. When in single-ended mode, +REF comes from the external reference voltage input. Generally, the power supply voltage +Vcc of ADS7843 is selected, and -REF is grounded, so the reference voltage is +Vcc. Assuming that the Y coordinate of the contact is obtained in this mode, since +Vcc is applied between Y+ and Y- through a transistor, the on-resistance of the transistor will always divide a part of the voltage. In this way, no matter where the contact is, it is impossible to obtain the full scale. This problem can be solved by working in differential mode. In this mode, when the Y coordinate of the contact is to be obtained, the chip automatically connects Y+ to +REF and Y- to -REF, so that the voltage between Y+ and Y- is always the reference voltage, eliminating the influence of the on-resistance of the transistor.

2.2 Digital Interface of ADS7843

The digital interface of ADS7843 includes five pins: chip select CS, serial data input DIN, serial data output DOUT, clock input DCLK, and interrupt signal PENIRQ. It can exchange data with a microcontroller or digital signal processor with a serial interface. It takes 24 serial clock cycles between the processor and ADS7843 to complete a complete conversion. The first 8 clock cycles are used to provide a control byte to ADS7843. The control byte is composed of the following:

When the S bit is "1", it indicates the start of the control byte; A[2:0] is used to select the quantization channel, "001" selects the X channel, and "101" selects the Y channel; when the MODE bit is "1", 8-bit quantization accuracy is selected, and when it is "0", 12-bit quantization accuracy is selected; when the SER/DFR bit is "1", the single-ended mode is selected, and when it is "0", the differential mode is selected; PD[1:0] is used to select a power saving mode. After the control word is transmitted, the next 16 clock cycles are used to transmit the quantized coordinate data.

The ADS7843 digital interface also has the following features: chip select is valid at low level, the clock is at low level when idle, and the rising edge of the clock samples serial data.

3 Touch screen driver design based on ColdFire processor QSPI interface

3.1 Hardware Circuit

The hardware connection diagram of the touch screen control chip ADS7843 and the ColdFire series processor is shown in Figure 4.

The four pins of the ADS7843 digital interface are connected to the corresponding pins of the COLDFire processor QS-PI module, and the interrupt signal pin PENIRQ is connected to the processor external interrupt pin IRQ4. Note that a 10kΩ pull-up resistor is required.

3.2 Software Design

The process from touch occurrence to obtaining the touch point coordinates is as follows: When a touch occurs, ADS7843 triggers an interrupt through the PENIRQ pin. In the interrupt subroutine, a delay of 10 to 20 ms should be first performed to remove the influence of jitter, and then a control word is sent to ADS7843 to obtain the X and Y coordinates.

To obtain the value of a coordinate, 24 clock cycles need to be input to ADS7843. For the QSPI module, these 24 cycles can be used as three 8-bit transmission queues, or one 8-bit and one 16-bit transmission queue. Here, three 8-bit transmission queues are selected. The QSPI initialization code is as follows:

Among them, QSPI_QMR and QSPI_QWR are the addresses of QSPI registers QMR and QWR. The winning X coordinate function code is as follows:

The function code for obtaining the Y coordinate is basically the same as that for obtaining the X coordinate. You only need to change the control command sent to ADS7843 to 0xD0, which means selecting the Y channel, 12-bit precision, and differential mode.

In order to observe whether the QSPI module and ADS7843 can communicate correctly, the timing of the four pins is captured using the Agilent1673G logic analyzer. Figure 5 shows the timing diagram when reading the X coordinate. The four pins are chip select CS, serial clock DCLK, serial data input DIN, and serial data output DOUT from top to bottom. It can be clearly seen from the figure that in the first 8 clock cycles, the processor inputs the control word to ADS7843; at the 10th clock, ADS7843 starts to output 12-bit quantized data; in the last 3 clocks, ADS7843 pulls the output line low.

Conclusion

The queue mechanism of the QSPI module speeds up data transmission and reduces CPU intervention. In addition, the module provides free configuration of clock valid level, sampling edge, chip select level, number of data bits transmitted, etc., so that it can flexibly communicate with various devices with serial interfaces.