Compact Image Acquisition System Based on ARM-EEWORLD

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OV7620 is a CMOS image sensor, which is widely used in webcams, camera phones and other products. The more common design method for the image acquisition system composed of it is to match OV7620 with OV511+ or CPLD/FPGA. The image data collected by OV511+ or CPLD/FPGA is output to PC or MCU (ARM, DSP, etc.) through USB bus or dual-port RAM, and the PC or MCU further processes the image data. The image acquisition system designed in this paper uses only one ARM chip to realize the function control, timing synchronization, data acquisition and processing of OV7620, and the system structure is compact and practical.

1 Hardware Structure

OV7620 is a CMOS color/black and white image sensor. It supports continuous and interlaced scanning modes, VGA and QVGA image formats; the maximum pixel is 664492, the frame rate is 30fp8; the data formats include YUV, YCrCb, and RGB, which can meet the requirements of general image acquisition systems.

The settings of the internal programmable function registers of OV7620 include power-on mode and SCCB programming mode. This system adopts SCCB programming mode, continuous scanning, and 16-bit RGB data output. The system hardware structure block diagram is shown in Figure 1.

Compact Image Acquisition System Based on ARM

The ARM chip uses LPC2210 with ARM7TDMI core, and the SCCB bus protocol is simulated through the GPIO of LPC2210 to control the function register of OV7620. The three interrupt pins of LPC2210 are used to introduce the image output synchronization signals VSYNC, HSYNC, and PCLK of OV7620, and the image data output is synchronized in interrupt mode. The 16-bit parallel data output by the YUV channel of OV7620 is connected through the high 16-bit data line of LPC2210. SST39VF160 and IS61LV25616AL are extended Flash and SRAM, which are used as program memory and data memory respectively.

2 Specific Implementation

2.1 Functional Control of OV7620

The control of OV7620 adopts SCCB (Serial Camera Control Bus) protocol. SCCB is a simplified I2C protocol. SIO-1 is the serial clock input line, and SIO-O is the serial bidirectional data line, which are equivalent to SCL and SDA of I2C protocol respectively. The bus timing of SCCB is basically the same as that of I2C. Its response signal ACK is called the 9th bit of a transmission unit, which is divided into Don't care and NA. The Don't care bit is generated by the slave; the NA bit is generated by the host. Since SCCB does not support multi-byte reading and writing, the NA bit must be high. In addition, SCCB does not have the concept of repeated start. Therefore, in the read cycle of SCCB, when the host sends the on-chip register address, it must send a bus stop condition. Otherwise, when sending a read command, the slave will not be able to generate a Don't care response signal. [page]

Due to some subtle differences between I2C and SCCB, GPIO is used to simulate the SCCB bus. The pin connected to SCL is always set to output mode, while the pin connected to SDA can dynamically change the input/output mode of the pin by setting the value of IODIR during data transmission. The write cycle of SCCB directly uses the write cycle timing of the I2C bus protocol; while the read cycle of SC-CB adds a bus stop condition.

The address of the OV7620 function register is 0x00～0x7C (many of which are reserved registers). By setting the corresponding registers, the OV7620 can work in different modes. For example, to set the OV7620 to continuous scanning and RGB raw data 16-bit output mode, the following settings are required:

I2CSendByte() is a register write function. Its first parameter OV7620 is the macro-defined chip address 0x42, the second parameter is the on-chip register address, and the third parameter is the corresponding register setting value.

2.2 OV7620 clock synchronization

OV7620 has four synchronization signals: VSYNC (vertical synchronization signal), FODD (odd field synchronization signal), HSYNC (horizontal synchronization signal) and PCLK (pixel synchronization signal). When continuous scanning is used, only three synchronization signals, VSYNC, HSYNC and PCLK, are used, as shown in Figure 1. In order to detect the effective size of the OV7620 scanning window, the HREF horizontal reference signal is also introduced.

The three external interrupt pins of LPC2210 are used as the input of three synchronization signals, and the corresponding interrupt service routines are Vsync_IRQ(), Hsync_IRQ() and Pclk_IRQ(). A two-dimensional array is defined in the memory to store image data. The first dimension is represented by variable y, which is used to count the horizontal synchronization signal; the second dimension is represented by variable x, which is used to count the pixel synchronization signal. The basic process of image acquisition is as follows: after initializing OV7620 with SCCB, enable the interrupt corresponding to VSYNC, and determine whether a frame of data has been obtained in the Vsync_IRQ() interrupt service routine. If so, data processing is performed in the loop body of the main program; if not, enable the interrupt corresponding to HSYNC, and set y to 0. In the Hsync_IRQ() interrupt service routine, determine the effective level of HREF. If valid, y is increased by 1, x is set to 0, and the interrupt corresponding to PCLK is enabled. In the Pclk_IRQ() interrupt service routine, determine the effective level of HREF. If valid, z is increased, and the image data of a pixel is collected at the same time. [page]

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2.3 Image data output speed matching

Among the three synchronization signals of OV7620, PCLK has the shortest cycle. When OV7620 uses a 27 MHz system clock, the default PCLK cycle is 74 ns. However, the interrupt response time of LPC2210 is much longer than this value. The maximum interrupt delay time of LPC2210 is 27 processor instruction cycles, and the minimum delay time is 4 instruction cycles. Adding the interrupt service time, field recovery time, etc., the time to complete an interrupt response is greater than 7 to 30 instruction cycles. When LPC2210 uses the highest system frequency of 60 MHz, its interrupt response time is much greater than 0.2 to 0.6 μs, so the PCLK of OV7620 can only be reduced. By setting the clock frequency control register, the PCLK cycle can be set to about 4 μs.

2.4 Image Data Access

When OV7620 works in master mode, its YUV channel will continuously output data to the bus. If the YUV channel of OV7620 is directly connected to the DO~D15 data bus of LPC2210, it will interfere with the data bus and make LPC2210 unable to operate normally; if the method of isolating and using the data bus in time by using 74HC244 etc. is used, the system operation speed will be greatly reduced, making it impossible for LPC2210 to take the data on the bus in time, resulting in incomplete image data. Since the data bus width of LPC2210 is 32 bits, and Flash and SRAM only occupy the lower 16-bit data lines D0~D15, the method in Figure 1 can be used to set the idle upper 16-bit data lines D16~D31 as GPIO to collect the 16-bit image data output by OV7620.

2.5 Image Data Recovery

When OV7620 uses 16-bit output mode, the data output format of the Y channel and UV channel is listed in Table 1. As can be seen from Table 1, the Y channel and UV channel of each row alternately output the repeated data of the previous row and the new data of the current row. Within a row, B data only appears in odd columns, and R data only appears in even columns.

Compact Image Acquisition System Based on ARM

The following takes a 55-pixel matrix as an example to introduce image data recovery in detail.

First, define a 515 byte array, and read the image data of 55 pixels in the Pclk_IRQ() interrupt service program; then interpolate the image data, and store B, G, 0 in the three consecutive bytes of the array for odd points, and store O, G, R for even points; finally, average each byte of the current row and each byte of the corresponding column of the next row to calculate the RGB value of the current row. In each row, the R data of the odd points and the B data of the even points can be obtained by averaging the R and B data of the two points on both sides.

In this way, an image is restored. It can be directly saved as a binary file (this system uses the serial port to output to the PC for display), or add the BMP bitmap file header information and save it as a DIB bitmap file with biBitCouNt=24; LPC2210 can also be used to further process this image data, such as fingerprint recognition.

3 Conclusion

The image acquisition speed of this system is mainly limited by the interrupt response time of LPC2210. If an ARM chip with a DMA controller and higher processing speed is used, the speed of the entire image acquisition system can be greatly improved. For example, the S3C2410 with an ARM9 core has a maximum system frequency of 203 MHz and the time to complete a DMA transfer is about 30 ns. This is shorter than the default PCLK cycle of 74 ns, and an image acquisition speed of 30 fps can be achieved.

Compared with the image acquisition system with OV511+ or CPLD/FPGA, this image acquisition system greatly simplifies the system structure, reduces the system design cost, and shortens the development cycle; the acquisition and processing of image data are completed by the ARM chip, thus reducing the probability of transmission errors during data transfer and improving the reliability of the system.

Keywords：ARM7 Reference address：Compact Image Acquisition System Based on ARM

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