Fetal ECG signal data acquisition system based on ARM

1 Introduction

Fetal electrocardiogram (FECG) is an objective indicator of the electrophysiological activity of the fetal heart, reflecting the growth and health of the fetus during pregnancy. The extraction and analysis of perinatal fetal electrocardiogram can determine the fetal heart rate and fetal cardiac function parameters, and timely detect pathological conditions such as fetal intrauterine hypoxia during pregnancy or delivery, so as to take measures as early as possible to ensure the health of the fetus. However, since the measured original signal components are very complex and the interference is serious, the fetal electrocardiogram signal is submerged in the strong background noise (especially the maternal electrocardiogram interference), which makes it very difficult to extract the fetal electrocardiogram. Therefore, it is of great theoretical value and clinical application value to study how to accurately and effectively extract the fetal electrocardiogram signal from the abdominal wall electrodes of pregnant women.

Due to the special influence of physiological phenomena and bioelectric signals during the fetal pregnancy period, the fetal ECG signal recorded in the mother's abdomen is quite weak and almost drowned in strong noise. The fetal ECG overlaps with the mother's ECG (MECG) in the time domain and frequency domain, and has strong randomness and non-stationarity. What method is used to eliminate interference, extract the fetal ECG waveform, and obtain lossless fetal ECG signal is the key to the problem. This system uses the 32-bit low-power microprocessor S3C44B0X based on the ARM core as the core, with electrodes, high-amplification amplifiers and high common-mode rejection ratio amplifier circuits to obtain real-time mother-infant ECG signals; under the embedded operating system uC/OS-Ⅱ, the mixed signals obtained from the mother are processed to realize the data acquisition, separation and display of the fetal ECG signal, thereby obtaining a single fetal ECG signal with little noise interference.
2 System design and working principle

The system structure based on S3C44B0X is shown in Figure 1. Its working principle is as follows: First, the mixed ECG signals of the mother's chest and abdomen are obtained through medical Ag-AgCl electrodes, and the signal conditioning circuit amplifies and filters the bioelectric signals, and then A/D conversion is performed. Then, the collected data is separated by algorithm through a 32-bit microprocessor, and the fetal PQRS waveform is displayed in real time and the data is stored; the embedded real-time operating system (RTOS) µC/OS-Ⅱ coordinates the work of each functional module, making the system have high real-time and reliability. The structure is shown in Figure 1.

3 Hardware Circuit Design

3.1 Signal Conditioning

Signal conditioning mainly includes the lead part, preamplifier circuit, baseline drift stabilization circuit, bandpass filter, notch circuit and post-amplifier circuit, isolation circuit, and the block diagram is shown in Figure 2.

Since the fetal ECG signal is very weak, generally between tens of microvolts and hundreds of microvolts, and there is strong interference while detecting the bioelectric signal, this puts high demands on the design of the conditioning circuit
. This scheme design uses a total of 7 electrodes: two maternal chest lead electrodes as reference electrodes for separating the fetal ECG; two abdominal maternal-fetal mixed lead electrodes, used to collect the mixed ECG signals of the mother and the fetus; a common end electrode, as the common end of the chest and abdominal lead electrodes; the remaining two ground electrodes, as ground terminals. The interference sources are mainly 50Hz power frequency interference and the polarization voltage formed by the contact between the lead wire and the skin. Power frequency interference mainly exists in the form of common mode, with an amplitude of several volts or even tens of volts. The purpose of suppressing this interference is mainly to improve the common mode rejection ratio of the entire circuit; the polarization voltage is the DC voltage generated by the chemical half-battery between the measuring electrode and the organism, and the maximum can reach 300mV. This system uses AD's instrument amplifier AD620 as the system's preamplifier, with high input impedance, small offset temperature drift, high common mode rejection ratio, and low input noise. The AD620 amplification factor G is determined by a single resistor Rg, and the gain formula is G=1+（49.4 kΩ/Rg）. According to engineering experience, the preamplification factor is generally 6~10 times to prevent the preamplification circuit from saturation. The output of the integrated operational amplifier OP90 is fed back to pin 5 of the AD620 to prevent baseline drift. Since the fetal ECG signal is mainly concentrated in the 0.05~100Hz frequency band, a limiting circuit and a passive low-pass filter are designed before the preamplifier circuit. The former prevents the myoelectric pulse from damaging the preamplifier circuit, and the latter effectively removes various high-frequency interferences. However, 50 Hz power frequency interference and 35Hz myoelectric interference still exist within the frequency band, and are usually processed by a dedicated notch circuit. However, due to the characteristics of the analog device itself, it is impossible to achieve an ideal state, and the fetal ECG signal is weak, which may filter out some useful signals. For this reason, this system uses a software filtering method. The post-amplifier circuit mainly uses the integrated operational amplifier OP90, and the gain range can be set. The isolation circuit is mainly used to prevent human safety and achieve isolation from electrical equipment. At the same time, in order to avoid the formation of a closed loop between channels due to common grounding, each channel needs to be isolated before entering the A/D. Considering the relationship between noise, the isolation circuit is placed after the amplifier to isolate the amplified large signal, which can greatly reduce the noise introduced by the isolation amplifier. The core of this circuit is a switch capacitor coupling isolation amplifier ISO124, whose isolation resistance is as high as Ω or more, the isolation capacitance is only a few pF, and the nonlinearity is less than 0.01%, which is incomparable to other methods such as photoelectric isolation. The DC-DC module is used to make the front and rear interstage power supply independent, and π-type filtering is especially used to reduce the ripple interference of DC-DC. Because of the working mechanism of the switch capacitor, the switch capacitor isolation amplifier will have the ripple interference of the internal switching clock frequency superimposed on the output. In order to reduce this interference, a first-order second-order low-pass active filter is added after the isolation amplifier to filter out the interference of the switching frequency of 500 kHz. The specific circuit structure is shown in Figure 3. [page]

3.2 A/D acquisition and control

Considering the large amount of fetal ECG data collection and high real-time requirements, and in order to ensure the continuity of data flow, the system is specially set up with a data acquisition module with C8051F020 system-on-chip as the core. Through a dual-port RAM, the collected data is transmitted to the embedded main control processor, which coordinates and controls the entire system, mainly completing the system settings, issuing command instructions, monitoring the system working status, data storage, etc. The characteristics of C8051F020 are as follows: fast operation speed; multi-channel 12-bit and 8-bit A/D converters are integrated on the chip, with a sampling rate of 100 ksps; 64 KB Flash memory, 4KB internal data RAM and external 64 KB data memory interface, etc. The dual-port RAM uses IDT's first-in-first-out (FIFO) memory chip IDT7134 chip, with a cache capacity of 8KB and convenient interface. The structure is shown in Figure 4.

3.3 Embedded Microcontroller ARM Unit

The entire target platform is based on the S3C44B0X processor. Due to the large amount of data, this system has expanded the capacity of the 2MByte Flash device SST39VF160 to download the BIOS program for booting the system and initializing the system, the embedded operating system µC/OS-Ⅱ, the graphical interface system µC/GUI and the application program. The Flash ROM is mapped to Bank 0 of the S3C44B0X. When the system is powered on, the processor starts running by fetching instructions from the address 0x0000000 of the Flash ROM [1]. The 64MByte SDRAM chip HY57V641620HG, after the system is started, the BIOS moves the application program to the SDRAM for execution. A portion of the SDRAM is also used as the LCD display buffer (video memory), and the rest is used to store temporary data, stacks, etc. The SDRAM is mapped to Bank 0 of the S3C44B0X. 6, which is the address of OxC000000; 320×240 color LCD display, providing a good human-computer interaction interface, driven by the LCD controller built into the S3C44B0X; 4×4 keyboard, for operating and controlling the entire terminal.

4 System Software Design

The software design mainly includes: transplantation of µC/OS-Ⅱ on S3C44B0X, fetal ECG data collection and storage, LCD display and keyboard program. This system uses the reentrant code compiler EmbestIDE Pro for ARM. [page]

4.1 Porting µC/OS-Ⅱ to S3C44BOX

µC/OS-Ⅱ is an embedded operating system with open source code. It is a priority-based preemptive real-time multitasking kernel. The code is written in ANSI C and has strong portability and good scalability. µC/OS-Ⅱ provides the basic functions required by real-time systems, including task scheduling, task management, time management, communication and synchronization between tasks, and memory management. It always executes the task with the highest priority in the ready condition and can manage up to 64 tasks. It dynamically manages large continuous blocks of memory by partition, which can effectively solve the problem of memory fragmentation. During the porting process, only some processor-related codes need to be modified, including:

(1) The processor header file OS_CPU.H, which includes processor-related variables, macros, and definition types defined using #define;

(2) Write four simple assembly language functions in OS_CPU_A.ASM: OSStartHighRdy(), OSCtxSw(), OSIntCtxSw(), and OSTickISR(), which are used to start the currently ready task with the highest priority, switch between tasks, execute the switching function from the ISR, and the clock tick ISR function respectively;

(3) Write the task stack initialization function OSTaskStInit() and five HOOK() functions that must be declared but do not need to contain code in OS_CPU_C.C.

4.2 Application Design

According to the characteristics of the fetal ECG acquisition system, the main tasks of the system are divided into the following: system monitoring task (priority 4), key scanning task (priority 5), LCD display refresh task (priority 6), storage task (priority 7), and priorities 0, 1, 2, and 3 are reserved for system use. After the system is initialized, µC/OS-Ⅱ schedules and executes tasks according to priority and ready state. The initialization work includes initializing all data structures, allocating stack space, establishing tasks and semaphores, message queues, and priorities for inter-task communication. After running the OSStart() function, the system monitoring task with the highest priority is run first to query whether other tasks send messages to it. If not, the monitoring task is suspended. At this time, the keyboard scanning task switches from the ready state to the running state. After the task is executed, if a key operation is detected, a message is sent to the response task to make them enter the ready state, and a message is sent to the monitoring task to indicate that this task is working normally, and the delay function OSTimedly() is called to make the task enter the suspended state. Since the monitoring task receives the message, it will enter the running state again and re-query the running information of other monitored tasks. If not, it will enter the suspended state. At this time, other tasks with relatively high priority in the ready state begin to execute. When the keyboard delay time is up, the system kernel automatically transfers the task to the ready state. If an abnormality occurs during operation, the monitoring task will handle it accordingly according to the set processing table to ensure smooth operation of the system.

5 Conclusion

The fetal ECG signal data acquisition system designed in this paper is improved and experimented on the basis of Embest S3CEV4O development board, making full use of its own hardware resources, and developing applications based on the real-time operating system µC/OS-Ⅱ to display and store fetal ECG data.

The author's innovation in this article is to rationally and effectively design the fetal ECG signal extraction circuit, combine the advantages of the ARM microprocessor itself, and perform algorithm separation, which has good engineering significance.