[Practical sharing] Detailed explanation of high-voltage CV test of MOSFET devices

The switching speed of semiconductor devices such as MOSFETs, IGBTs and BJTs is affected by the capacitance of the component itself. In order to meet the efficiency of the circuit, the designer needs to know these parameters. For example, designing an efficient switching power supply will require the designer to know the capacitance of the device, as this will affect the switching speed and thus the efficiency. This information is usually provided in the MOSFET specification sheet.

Figure 1. Component-level capacitance of a power MOSFET.

The capacitance of a three-terminal power semiconductor device can be viewed at two different levels: component and circuit. Viewing capacitance at the component level involves characterizing the capacitance between each device terminal. Viewing capacitance at the circuit level involves describing the combination of component-level capacitances. For example, Figure 1 illustrates the component-level capacitance of a power MOSFET. Figures 2 through 4 illustrate the relationship between the component-level and circuit-level capacitances of a power MOSFET. Similar capacitance measurements can be made for BJT and IGBT devices.

The relationship is as follows:

• CISS = CGS + CGD = Input Capacitance

• COSS = CDS + CGS = Output Capacitance

• CRSS = CGD = Reverse transfer capacitance

Figure 2. Input capacitance of a power MOSFET Figure 3. Output capacitance of a power MOSFET Figure 4. Reverse transfer capacitance of a power MOSFET

The capacitance of a device typically varies with the applied voltage. Therefore, a complete characterization requires knowledge of the capacitance at the maximum rated voltage. This application shows how to use the biasing capabilities provided by the 4200A-CVIV switch and measure CISS, COSS, and CRSS in Clarius. CVIV makes it easy to switch between IV and CV measurements, and it also allows CV measurements to be moved to any device terminal without reconnecting or lifting the probes.

This article also shows how the instrument's DC output voltage can be increased from 200V to 400V to allow for higher voltage measurements on the drain, which is useful for testing higher power semiconductors such as GaN devices. This feature has been added and updated in Clarius V1.6 and above.

1. Device connection

All SMU and CVU connections described in this article are made through the 4200A-CVIV. The CVIV can have either a 4210-CVU or 4215-CVU, allowing up to four SMUs to be connected to one device. Using the 4200A-CVIV provides the following advantages:

• Built-in items measure CISS, CRSS, and COSS up to 200V and 400V.

• The 4200A-CVIV switch allows for automatic measurements. No rewiring of equipment or cables is required.

• CV compensation for open and short circuits.

Figure 5 shows the connections of the MOSFET to the CVIV. For this particular application, at least three SMUs and one CVU are required to complete the test. Figure 6 shows the actual CVIV connections for the packaged MOSFET. Note that all channels on the CVIV are open. The four channels of the 4200A-CVIV will be configured based on the configuration for each test, so no cable reconnection is required for each test.

Figure 5. MOSFET connected to the output of the 4200A-CVIV Figure 6. Packaged MOSFET connected to the 4200A-CVIV

2. Configuring Measurements in Clarius Software

Clarius' library has two projects that perform three-terminal capacitance measurements on MOSFETs. The two projects are configured similarly in Clarius, differing in capabilities. One project, "MOSFET 3-terminal CV Test Using 4200A-CVIV Bias Tees," uses a single SMU applied to the drain terminal to sweep from 0 to 200V DC bias voltage. The other project, "MOSFET 3-terminal CV tests up to 400 V using 4200A-CVIV Bias Tees," uses a new method to sweep from 0 to 400V. This method uses three SMUs to sweep simultaneously, one on each device port, to provide a 400V DC differential voltage.

Figure 7. MOSFET-CVIV-CV-Bias-Tees project using the SweepV User Module

Figure 7 shows the “MOSFET 3-Terminal CV Test Using 4200A-CVIV BiasT” project, which uses the SweepV user module from hivcvulib. This user module allows a single sweep at the drain and capacitance measurements at each port of the device. First, open and short compensations are performed to ensure accurate measurements. There are specific configuration steps required to perform these compensations. They are called compensated measurements and are available in the project tree. Compensation is performed for each test before any test is performed. The 4200A can store compensation for each configuration and multiple tests can be performed. There are five different configurations for this project: CISS, CRSS, COSS, CGS, and CDS.

CVIV Configuration

CVIV must be configured for each test. CVIV has many output modes, which are described in the user manual. Table 1 lists the various output modes.

Table 1. 4200A-CVIV Output Modes

Figures 8 to 12 show the status of each channel of CVIV for each component and circuit-level capacitance measurement.

Figure 8 shows the CGS configuration, which measures the capacitance between the gate and source of the MOSFET as the SMU sweeps a DC voltage at the drain. Figure 9 shows the CDS configuration, which measures the capacitance between the drain and source as the SMU sweeps a DC voltage at the drain. Figure 10 shows the CRSS configuration. This test measures the reverse transfer capacitance of the MOSFET as the SMU sweeps a DC voltage at the drain.

Figure 11 shows the configuration of the CISS test, which measures the input capacitance of the MOSFET while the SMU sweeps a DC voltage. Figure 12 shows the COSS configuration, which measures the output capacitance of the MOSFET while the SMU sweeps a DC voltage at the drain. Once the test is executed, the data is plotted. Figure 13 shows the capacitance characterization data of the MOSFET generated by the 4200A.

Figure 13. Capacitance characteristics of MOSFET swept to 200V

3. 400V DC voltage scanning

A new method to double the output voltage of a MOSFET device to 400V by simultaneously sweeping multiple SMUs with the 4200A-CVIV Multi-Switch. These tests are usually done in the OFF state (VGS = 0V). There is usually one sweeping SMU at the drain, using the built in biasing capability of the 4200A-CVIV to measure the capacitance at each terminal.

Figure 14. Three SMUs scanning simultaneously

Figure 14 shows three sweeping SMUs connected to the three ports of a MOSFET. SMU1 and SMU2 will use a differential voltage of up to 400V. SMU2 and SMU3 must sweep simultaneously at the same voltage, which can drop the gate to 0V. Using this method, we can generate a 400V sweep voltage at the Drain terminal. This method is only used for packaged devices and not for wafer-level devices.

These measurements were performed using the multiple SMU_SweepV user module, available in the hivcvulib user library.

Figure 15. Projects with outputs up to 400V DC differential

Figure 15 shows the 4200A-CVIV Bias Tee project using the Multiple SMU_SweepV user module to perform a three-port CV test of a MOSFET up to 400V. The project tree is set up in the same manner as the previous project. All CVIV configuration operations, including compensation, are done in exactly the same manner. The only difference is that two additional SMUs must be configured. By default, the test should be swept from 0 to 400V on the Drain. The Gate and Source SMUs should be swept at the same voltage at the same time. The user is also able to change the CVU settings such as frequency, range, and speed depending on the impedance of the device under test.

Figure 16. Capacitance characteristics of MOSFET swept to 400V

Figure 17. Output data for 400V sweep

Figure 16 shows a CV sweep up to 400V on the MOSFET being tested in the 4200A-SCS. The differential voltage is a calculated value. The difference is the voltage between the drain and source. Figure 17 shows the output data, which lists the swept voltages at the three ports. Diffvoltage is the calculated differential voltage value.

IV. Conclusion

The switching speed of semiconductor devices such as MOSFETs, IGBTs and BJTs is affected by the capacitance of the component itself. This application shows how the 4200A-CVIV can be used to make these measurements at 200V DC bias without the need to reconnect any cables, thus reducing user error and allowing automated testing. It also allows the circuit level capacitance to be measured directly without having to go through the component level capacitance, which allows the circuit level designer to get the data they need faster.

Additionally, when measuring capacitance on a three-terminal device, there is usually one terminal not included in the measurement whose capacitance may affect the overall measurement. Using a bias network at each port eliminates the effects of external capacitance or shorts.

We also demonstrated a new method to double the DC bias of the 4200A on a three-terminal device by sweeping it with three SMUs simultaneously. The gate and source SMUs are swept simultaneously in the same polarity to avoid the effects of the on-state of the device. The drain SMU will sweep the opposite polarity of the source and gate, doubling the differential voltage. This supports voltage sweeps up to 400V at the drain, which is beneficial for testing higher power semiconductors such as GaN.