Interface design and application of plasma display screen GU128×64

    Abstract: This article introduces the characteristics and peripheral interface circuits of the plasma display screen GU128×64, as well as the fault display system composed of GU128×64, ATMEL89C51, etc. The hardware interface circuit and part of the software programming of the application system are given. The entire fault display system has the following diagram: It has the advantages of clear image, stability and reliability.

    Keywords: plasma display screen AT89C51 microcontroller

When designers develop systems, they always hope to choose the most ideal, highest quality, and most satisfactory devices for the products they design. In particular, display devices used to display information receive even greater attention. Because the display device is the face of the instrument, it needs to be beautiful, decent, and generous, and it also needs to be able to transmit information accurately, clearly, and reliably. In situations where various graphics and text information are required to be displayed eye-catchingly, clearly, and with a large viewing angle, general LCD displays are difficult to satisfy due to their small viewing angles and limited brightness, and their advantages such as low voltage and micro power consumption are useless. The place of martial arts. Due to its characteristics of clear display, stable signal, large display area and simple interface, the plasma display screen can overcome the above shortcomings and is very suitable for occasions with high display requirements.

The plasma display screen is a large-screen display system using a plasma display panel (PDP) as the display device. It uses inert gas to discharge in a vacuum to generate ultraviolet rays to excite red, green, and blue phosphors to form Color display. It can assemble multiple PDPs together to form a display screen of several square meters to display various texts and images. Plasma display screens are developing rapidly outside Luowai, but there are no related products and application reports in China. This article introduces the characteristics and interface circuit of the GU128×64 plasma display screen launched by Japan's ISE ELECTRONIC CORP., and briefly explains the software and hardware design points of the system based on application examples.

1 GU128×64 plasma display

The GU128×64 plasma display screen is composed of a 128×64 dot matrix graphics VFD, VFD driver, DC/DC converter, display memory, display controller and its corresponding control logic circuit. Its input is CMOS level, there are two working voltages +5V or +12V, its working temperature: -10℃～--+65℃; temperature; 20%～85%RH. Table 1 shows the general specifications of GU128×64 plasma display zero, and Table 2 shows its interface signal description.

Table 1 General specifications of GU128×64 plasma display screen

Table 2 Interface signal description

The GU128×64 dot matrix plasma display screen includes static memory corresponding to the four-page screen, circuits that control RAM reading and writing, and VFD. The following is an introduction to each interface signal:

D0～D7: Data input bus, also used as data input for brightness control;

A0～A9: input address lines;

READY: Data ready signal, "0" READY enables, "1" READY disables;

CLEAR: One of the functions is to clear the static storage page by selecting WP0 and WP1; the other function is to turn off the display. This input has priority over other control inputs;

WRITE: When WRITE is low level, the data input or brightness control input is valid;

WP0, WP1: Select the written static storage page, (WP0, WP1) = (0,0): Select the first page

(WP0, WP1)=(0,1): Select the second page

(WP0, WP1)=(1,0): Select the third page

(WP0, WP1)=(1,1): Select the fourth page

DP0, DP1: Select the display page, (DP0, DP1) = (0, 0): Select the first page

(DP0,DP1)=(0,1): Select the second page

(DP0, DP1)=(1,0): Select the third page

(DP0, DP1) = (1, 1): Select the fourth page

DSPE: Display enable control input. When the DSPE input is low, the display is turned off and all operations on the memory page are no longer effective;

LAMP TEST: brightness test input. When the level is low, all dot matrices are turned on but have no effect on the memory page; when the level is high, the display mode is normal.

Brightness control: When BRAD=0, the brightness control of the plasma display screen is carried out through the combination of D0 and D1. The default condition is 100% normal brightness.

(D, D0)=(0,0): 25% of normal brightness;

(D1, D0) = (0,1): 50% of normal brightness;

(D1, D0) = (1,0): 75% of normal brightness;

(D1, D0) = (1,1): 100% of normal brightness;

The timing sequence of GU128×64 plasma display screen is shown in Figure 1.

2 Interface design between GU128×64 and microcontroller

The interface between GU128×64 plasma display zero and AT89C51 is shown in Figure 2. The P1 port of 89C51 serves as the input of 24 switching signals. The system completes the switching of three 8-channel signals by controlling P3.3, P3.4, and P3.5. 74LS373 latches the address information transmitted from the P0 port of 89C51. The data lines D7~D0 of GU128×64 are directly connected to the P0 port, and the other control signal lines are connected to the P2 port respectively.

3 Software design

In general, software programming for GU128×64 is relatively simple, but graphics and curve display still require certain skills. The software design idea of ​​the system is: after the system is powered on and reset, 89C51 first initializes and clears the GU128×64 plasma display screen, then displays normal working text and graphics, and then performs P3.3, P3.4, and P3.5 Carry out cycle gating control respectively to determine whether the 24 input signals are abnormal. If abnormal, the corresponding fault information and graphics will be displayed; otherwise, normal information will be displayed.

Given below is part of the display program for a plasma display screen:

******* R0——RAM Address *******

******* R1——Bytes to Display *******

******* A——Table offset address *******

******* DPTR——Table Base Address *******

…

DISPLAY：

CJNE R1, #00H, WAY1

LJMP WAY2

WAY1:

JB READY, $ determines whether the display is ready

SETB CPADDR outputs the RAM address of the display screen

MOV BUS, R0 enables 74LS373

CLR CPADDR

PUSH ACC Enter data into the display

MOVC A, @A+DPTR Look up the table to get the required prompt information

MOV BUS,A

CLR WRITE WRITE signal enable of display screen

POP ACC

INC A

SETB WRITE

DEC R0

DJNZ R1, WAY1

Way2:

RET

…