SoC-based digital camera system

    Abstract: This article focuses on the working principle and internal circuit of the SoC-based digital camera system. Finally, a brief description of its chip and system performance is provided.

    Keywords: Embedded system digital camera (DSC) SoC

1 Overview

The biggest feature of digital cameras is signal digitization. It uses an imaging chip CCD to decompose still or moving images into pixels and convert them into electrical signals. These signals are converted into digital signals by the digital signal converter in the digital camera, and then are sent to the internal or external memory through image processing and data compression encoding by the microprocessor, and can also be sent to the LCD/TV display screen.

The digital information in the memory is input into the computer through the interface and then turned into an image. With the help of the image processing software provided by the CPU, processing, editing, etc. are carried out according to people's wishes, and then an ideal image is produced by a color printer. What's more, the digital committee can also be spread around the world through computer networks.

*Images are stored digitally for easy storage, transfer and reuse, eliminating the need for film development and image enlargement.

*You can use a computer to modify, edit and other processing of images, and you can also input them to TV and watch online.

*Can be transmitted over long distances through computer networks, and has the advantages of fast speed, low interference, and high quality.

The digital camera system introduced in this article is composed of a single-chip large-scale integrated circuit LSI. It can transmit full-motion images or continuous images at a rate of 30 frames/s, and has small size, low power consumption, fast transmission speed, and high resolution. specialty.

2 Working principle

The principle of the digital camera system is shown in Figure 1. The system consists of a CCD signal processor, M-JPEG codec, 32-bit RISC-CPU, NTSC encoder, DRAM controller and various peripheral interfaces. It is a typical embedded system.

The signal from the CCD, after color-corrected Y/C separation, is converted into a 10-bit digital signal through the A/D converter and written into the frame buffer in the dynamic memory DRAM as a YUV (4:2:2) image data. These data are sent to the NTSC/PAL encoder for encoding, and finally displayed on the LCD display. When the shutter is released, these data are also sent to the M-JPEG chip, and are stored in the JPEG encoding area in DRAM after 1/10 and 1/20 compression encoding. RISC-CPU converts the compressed data into file format data and then writes it to external memory, such as a microdrive. During playback, the data flow is opposite to the above (photography). The decoded image is displayed on the LCD display.

The system uses three-bus separation technology, which separates the signal bus (228 MB/s), CPU bus (114 MB/s) and peripheral bus (57 MB/s), using a RISC chip (32-bit embedded microprocessor) It can process signals effectively and at high speed to avoid the contradiction between the need to store large-capacity image data and the slow processing speed of peripherals. This bus separation technology can not only solve the problem of communication congestion, but also achieve high-speed and high-resolution image processing, which is an important feature of the system.

3 several important circuits

3.1 CCD signal processing circuit

In order to process the signal of 1360×1042 (1.5M) pixels in real time, the circuit uses pixel primary color progressive scan CCD camera technology. The CCD signal processor is a key circuit in a digital camera (DSC), and its quality will directly affect the performance of the DSC. The circuit consists of a raw data calibration module, a color processing module, a digital amplification module, an RGB-YUV conversion module and an image quality adjustment module, as shown in Figure 2. The original data calibration module consists of digital clamping, pixel calibration white balance, automatic forcing and gamma calibration circuits.

Utilizing 4 line memories, the color processing module can convert raw CCD data into RGB data. In order to reduce the capacity of the line memory, a new scanning technology is used in the signal processing module to divide the image frame into several small blocks and scan each small block respectively.

Compared with ordinary CCD signal processing circuits, this circuit has the following characteristics:

(1) Only 4 line memories are needed to achieve high-quality and high-speed image enlargement processing.

(2) Firmware settings with software functions can fine-tune image quality.

(3) Use the pipeline method to complete CCD real-time signal processing. During real-time processing, only after the data is sent to DRAM, the original data from the CCD is converted into YUV data.

3.2 M-JPEG encoding and decoding circuit

This system uses a new motion JPEG encoding and decoding technology, which can compress, encode and decode VGA (350×10 3 pixels) images at a rate of 88 frames/s under 57MHz clock conditions. This new encoding technology has the following advantages:

(1) Each image is independent and easy to limit and edit;

(2) Compared with MPEG, JPEG requires less circuits and can significantly reduce power consumption and cost.

The M-JPEG encoding and decoding circuit is shown in Figure 3. As seen in Figure 3, the circuit consists of 5 modules. When encoding is performed, the data flows to the left; when decoding is performed, the data flows to the right. If high-speed pipeline processing is performed on modules with 8×8 pixels as units, the new M-JPEG encoding and decoding technology can be used to encode and decode VGA, XGA, and 1.5M images at different rates.

The rates of M-JPEG encoding and decoding are listed in Table 1.

It can be seen from Table 1 that when the operating frequency or clock frequency is 57MHz, when using the new method to encode and decode VGA pixels and 1.5M images, their rates are 88 frames/15 frames/s respectively, which is higher than the past Method is 4 times faster. This not only enables DSC to perform high-speed image capture and real-time processing, but also greatly saves overall encoding time.

Table 1 M-JPEG codec rate

3.3 RISC CPU

RISC CPU is the core circuit of the single-chip digital camera system. It is a 32-bit RISC embedded microprocessor. The circuit contains 4KB of digital memory, 4KB of program memory and multiple accumulators, and can operate at a frequency of 576MHz. In the DSC system, the RISC CPU can handle image editing, real-time camera control, sound recording/playback, image file generation and various software controls.

3.4 Three-bus structure

In order to be able to perform high-speed, high-resolution real-time processing of images, this system uses three-bus separation technology. The first bus is called the signal bus, which has the highest transmission rate (228 MB/s) and is connected to the image processing device. The second bus is called the CPU bus, which is a CPU local bus with a moderate transfer rate (114 MB/s). It can be connected to the signal bus through the CPU bus. Can directly access DRAM. The third bus is called the peripheral bus, which has the lowest transmission rate (57 MB/s) and can be connected to peripheral circuits that work at low speeds.

3.5 Power management

In order to save power, this system uses two power management technologies: one is clock frequency adjustment technology; the other is clock suspension control technology.

The clock suspension control technology is to suspend the clock feed in non-functional functional modules and divide the clock into 27 parts. According to the camera working mode, the function module and firmware are used to change the suspend clock, thereby reducing the power consumption of the entire system.

In addition, the chip uses different power supply technologies, that is, the chip is powered internally by a low power supply voltage (2.5V), while the I/O pins are powered by a 3.3V power supply. This power supply technology can also greatly reduce the power consumption of the power supply.

4 performance

4.1 Performance of a single chip

The single chip of this system is a relatively new large-scale integrated circuit LSI, and its main performance is listed in Table 2.

Table 2 Main performance of the chip

4.2 Performance of single-chip digital cameras

Using a single chip to form a camera is a typical application of SOC (System on Chip). The main performance of the camera is listed in Table 3.

Table 3 Main performance of DSC