Key requirements in high-speed signal generation applications

bandwidth

In any signal generation application, the most important design criterion is bandwidth. The first question any designer asks is: How much bandwidth is needed to generate the desired signal? For a specific signaling protocol or a specific application, the designer may need a certain amount of bandwidth. Regardless of the bandwidth the designer wants to achieve, the speed of the DAC must be at least twice the desired bandwidth. This relationship between bandwidth and sampling rate (fs) was defined by Harry Nyquist and describes how the signal behaves in a sampled system.

Although it is possible to generate signals with bandwidths from DC to fs/2, it is often not practical to do so because images of the generated signal will appear in the output spectrum. The images will appear at N×fs±fout (where fout is the frequency of the generated signal). In practice, reconstruction filters are required to attenuate any images of the generated signal that may appear in the output spectrum. Even if the bandwidth of the generated signal does not extend to fs/2, but is close to it, the images will be difficult to filter out. Reconstruction filters are implemented in the analog domain using real components. Unlike digital filters, these components are non-ideal, resulting in non-ideal passbands with ripple and insertion loss. In general, the higher the order of these filters, the greater the ripple and insertion loss, making it more difficult to design an ideal filter. The closer the signal bandwidth is to fs/2, the higher the filter order must be to attenuate the images generated by the sampling process. The higher the filter order, the more components are required, resulting in greater insertion loss and passband ripple.

Figure 1: LTC2000 proposed schematic.

Using a DAC with a higher sampling rate will increase the available bandwidth, which will reduce the requirements on the filter, allowing the filter to use fewer components and reduce complexity, thus simplifying the design and producing better results. The LTC2000 is a high performance, 16-bit, 2.5Gsps high speed DAC with a 2.5Gsps sampling rate, so the fs/2 frequency is 1.25GHz. Therefore, for a signal bandwidth of 800MHz, there will be an image signal at 1.7GHz. There is 900MHz between the desired frequency band and the image signal frequency. With a guard band of 900MHz, the image signal can be easily filtered out with a simple low-pass filter. The image signal generated by the DAC with a lower sampling rate is closer to the desired frequency, so a more stringent and complex filter is required.

Another problem with generating signals with bandwidths extending to fs/2 is that any DAC has a SINC (sin(x)/x) roll-off that will attenuate the generated signal as frequency increases. This roll-off has a zero at the sampling frequency (fs), making it impossible to generate a signal that occurs exactly at the sampling frequency. The generated signal is simply a DC voltage. For practical purposes, approximately 60% of the Nyquist zone (DC to fs/2) does not have much SINC attenuation and can be used. If 0dB is the signal level at DC, then at 60% of the Nyquist frequency, the signal level has dropped by 6dB. The inverse of this roll-off is often implemented in the digital domain to correct for the natural roll-off of the generated signal. This allows the DAC to generate a waveform that has a constant amplitude with frequency. If a higher speed DAC is used, the roll-off of the SINC function is reduced as the DAC output frequency increases.

Phase Noise

Another important factor to consider in signal generation applications is the phase noise of the output. Phase noise present in the output signal limits the spacing between signals and can limit the number of modulation orders that can be achieved. In signal generation, the greater the phase noise, the lower the SNR of the generated signal and the higher its bit error rate. Jitter is a measure of the accuracy of the signal's zero crossings in the time domain. A perfect signal would cross zero at the same time in every cycle. In reality, these zero crossings will have some dispersion in time. If this dispersion is converted to the frequency domain, the phase noise can be seen as spectral leakage around the fundamental tone. If several tones are close together, the SNR of a tone can be degraded by the spectral leakage of its neighboring tones, which can worsen the signal's bit error rate and reduce the accuracy of the generated signal. This loss of signal integrity can be avoided by reducing the phase noise introduced in the generated signal.

The simplest way to avoid introducing phase noise into a signal generation system is to start with a very low phase noise clock. A clock with a lower phase noise imparts lower phase noise to the generated signal. It is also important to note that the attenuation of the clock phase noise added to the generated signal is proportional to the ratio of the generated signal frequency to the clock sampling rate. This proportional relationship means that if a low frequency signal is generated using the same clock, less phase noise will be generated on the output signal than if a high frequency signal is generated using a high sampling frequency clock. If the generated spectrum is wide, the generated signal will have more phase noise at the high end of the spectrum relative to the lower frequency end.

Figure 2: LTC2000 recommended layout.

The LTC6946 is a frequency synthesizer that can generate signals from 370MHz to 5.7GHz without an external VCO. The device has excellent phase noise performance and very low parasitic components, making it suitable as a clock source for signal generation applications. When the LTC6946 drives the LTC2000 high speed DAC, the phase noise generated is low enough for most demanding signal generation applications. The LTC6946 contains an internal VCO, which can make a trade-off between convenience and phase noise. If the LTC6945 and an external VCO are used, even lower phase noise can be achieved. For the LTC6945 and LTC6946 frequency synthesizers, the dominant phase noise source is the VCO. When generating a 65MHz output tone, the LTC2000 has -165dBc/rHz additive noise at 1MHz offset. This ensures that the clock phase noise dominates compared to the additive phase noise of the LTC2000 itself. In order to avoid other noises from degrading the output signal, proper layout methods should be used in the analog output circuit section.

Proper RF layout

The benefits of using high performance DACs and clock sources can be greatly reduced if proper design and layout rules are not used when designing the printed circuit board. Without proper symmetry, bypassing, and barriers, errors may occur in the resulting analog output waveforms, and noise and other parasitic components may be introduced. Figure 1 shows a typical schematic of the LTC2000. The LTC2000 has a noise spectral density of better than 158dBm/rHz for signals up to 500MHz, which helps maintain a high signal-to-noise ratio over a wide range of signal frequencies. The device's spurious-free dynamic range (SFDR) is better than 74dB up to 500MHz, and better than 68dB for output frequencies up to 1GHz. To maximize the performance of the LTC2000, proper layout is required. The outputs of the DAC should be treated as a differential pair and routed as symmetrically as possible. Any asymmetry in the output network can cause a voltage difference between the differential signals. This voltage difference will cause common-mode interference, which will produce unwanted distortion and noise in the output spectrum. This interference can be avoided by making the transmission lines of each output symmetrical.

Analog outputs can be protected from interfering signals by vias and good layout. Signal generating DACs have three ports and present layout challenges: clock input, analog output, and data input. If the data input traces are close to the output or clock, the data signal can couple into these signals, causing spurious noise in the output spectrum. Similarly, if the clock signal is coupled into the analog input due to poor layout, it will affect the integrity of the generated signal. When designing the board, the DAC can achieve the highest performance by setting up appropriate barriers between the digital circuits, clock signals, and analog output circuits. It is appropriate to route digital signals, clock signals, and analog outputs on different layers to minimize the interaction between these signals. Figure 2 shows the layout of the LTC2000 and shows how to isolate the digital signals, clock signals, and analog outputs. In this figure, the digital traces are routed on the inner layers of the board and are connected to the LTC2000 pads only through vias. The clock traces are very short, surrounded by vias to isolate the signal, and are not routed next to digital traces or analog outputs. Output traces should be as symmetrical as possible and surrounded by barriers that protect the analog outputs from interfering signals. By following these layout guidelines and using a clean sampling clock, the LTC6946 and LTC2000 can produce very clean waveforms that meet the needs of the most demanding signal generation applications.