Designing Ultra-Low-Power Embedded Applications: Simplifying Power Domains

　　Figure 3: High-level block diagram of the watch

　　A logical approach is to split the entire system into different subsystems and analyze the power consumption of each subsystem. This also helps in simplifying the design of the power domains to achieve low power consumption functions.

　　The power consumption of the display and touch controller part mainly depends on the backlight driver and the display itself. Most designs use a timer-based timeout power-down mode for the display. Generally speaking, after a fixed time T1, the backlight will drop to a 50% duty cycle, and after a time T2, the display will be completely turned off. At this time, even the touch controller can be turned off or put into power-down mode, depending on the usage scenario. In this way, the designer can draw a current curve for this functional block to obtain a typical current.

　　Wireless controllers (such as those for Bluetooth) are usually low power. Such controllers have some way of switching between high and low power modes. The typical values ​​in the wireless controller datasheet are the closest estimate of power consumption we can get without analyzing the system performance. However, we must remember to take into account the duty cycle of the device between different power modes.

　　Sensor current is primarily determined by the excitation current and the power consumption of the analog front end (AFE). Devices such as Cypress's PSoC 4 have built-in analog functions such as ADC and other AFE components, which allows designers to dynamically power down different functional blocks through firmware commands. This level of control and fine granularity can further improve the efficiency of low-power designs.

　　For complex designs involving multiple controllers and multiple operating modes, it is important to design the power circuit to accommodate different controllable power domains. In this way, a single controller on a standby power domain can effectively control other domains. This architecture may be more expensive, but it can maintain very low power consumption.

　　After identifying each subsection, the following methods can be used to optimize the power consumption of each subsection:

　　1. Turn off the regulator to turn off the entire subsection

　　2. Power off unused peripherals

　　3. Use the microcontroller’s low-power modes to reduce average power consumption

　　The most effective way to achieve low power consumption is to turn off the regulator used to power a given subsection. If a particular subsection does not need to be available for a long time and its function is not time-critical, its regulator itself can be controlled by the host controller. A sensor is a good example of a subsystem that can be turned off when the system is not operating. The only leakage current consumed will be the current of the regulator.

　　If it is not possible to power down the entire subsection, then consider the individual peripherals and components within the subsection. For example, in the sensor section, there may be some sensors that need to continue measuring and some that do not. Consider a thermistor that measures temperature, an accelerometer, and an IR sensor. The accelerometer needs to frequently check for activity, and the rest of the system needs to wake up accordingly. In contrast, the temperature sensor and IR sensor do not need to be active most of the time. Now let's talk about the excitation of the thermistor (see Figure 4). In this case, current will flow through the thermistor and reference resistor regardless of whether a measurement is being made.

　　Figure 4: Typical thermistor excitation circuit

　　Now, if the thermistor circuit is modified as shown in Figure 5, the current consumption can be avoided when the sensor is not being sampled.

　　Figure 5: Thermistor excitation for low power consumption

　　In this case, the pin is configured in strong output mode (CMOS inverter). When the sensor output is to be measured, the pin is driven low. This connects the thermistor to Vss through the NMOS transistor. The only additional resistance to consider is the on-resistance of the NMOS transistor, which is generally very low. When the sensor output does not need to be measured, the pin is driven high. This connects the thermistor to Vdd, resulting in zero current on the sensor circuit.

　　Since the accelerometer does not need to be sampled at all times, the ADC and other analog components (such as op amps or reference generators in the analog signal chain) can be powered down when the detection signal is not needed.

　　There are many other ways to reduce power consumption when implementing this circuit in an SoC, which we will discuss below. Consider the system shown in Figure 3, where the LCD controller can be put into hibernation mode and the host processor can wake it up when it senses an I2C command. When the circuit is implemented in PSoC 4, power consumption can be as low as 20 nA.

　　Likewise, if the sensor subsection is implemented with a low power mode and all components are turned off, the MCU can be woken up using a comparator interrupt in the event of motion. The accelerometer output can be connected to the comparator, ensuring that any motion wakes up the device and triggers an event to the host processor.

　　For systems built on SoCs, other techniques can be used to reduce average power consumption. For example, all peripheral clocks can be set to the slowest clock frequency, which can save power because dynamic power consumption is proportional to the switching frequency. As another example, the clock frequency of the ADC in the SoC should usually be proportional to the required sampling rate. If the ADC is set to a higher sampling rate than the actual system needs, it will cause unnecessary battery load.

　　There are other system-level techniques that can be used to reduce overall power consumption. For example, the device output can support a lower slew rate to reduce radiation. However, the lower slew rate causes the pin driver stage of the FET to consume more current because both the PMOS and NMOS are turned on for a longer period of time. Depending on the amount of radiation allowed in the system, the slew rate of the pin can be adjusted to a higher or lower level.

　　Choosing devices that offer multiple power modes, high levels of integration, and better control over the SoC's power state can simplify the implementation of low-power systems. Depending on the application, different power modes can be used effectively to ensure low average current. Although higher clock frequencies result in higher power consumption, temporarily running the CPU at high frequency and then returning the device to sleep more quickly can actually help achieve lower average power consumption. Developers should consider the overall system and avoid leakage current paths as much as possible.