Bandwidth Mismatch Between Interleaved ADCs

Publisher:EtherealHeartLatest update time:2014-04-23 Source: 21ICKeywords:ADC Reading articles on mobile phones Scan QR code
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Bandwidth mismatch between interleaved ADCs is probably the most difficult mismatch problem for designers to solve. As shown in Figure 1, bandwidth mismatch has both gain and phase/frequency components. This makes solving bandwidth mismatch more difficult because it has two components from other mismatch parameters: gain and timing mismatch.

 

 

Figure 1 Bandwidth mismatch

However, in bandwidth mismatch, different gain values ​​are seen at different frequencies. In addition, bandwidth has a timing component, causing signals at different frequencies to experience different delays through each converter. The best way to minimize bandwidth mismatch is to perform extremely good circuit design and layout practices that minimize bandwidth mismatch between ADCs. The better the match between ADCs, the fewer spurs will be generated.

Since gain and timing vary with frequency, any type of algorithm that attempts to calibrate out the errors is extremely complex. This may add too much circuit and area overhead to offset the benefits of calibration. Therefore, proper layout techniques can help reduce this type of mismatch and take into account the other types of mismatch (offset, gain, and timing), which also have a significant impact on interleaving spurs.

There are four major mismatches in an interleaved ADC, bandwidth mismatch, offset mismatch, gain mismatch, and timing mismatch, and these mismatches have something in common. Three of the four mismatches will produce spurs in the output spectrum at fS/2 ± fin. The offset mismatch spur is easy to identify because it is the only one located at fS/2 and can be easily compensated for. Gain, timing, and bandwidth mismatches all produce spurs in the output spectrum at fS/2 ± fin; therefore, the question is: how do you identify their respective contributions? Figure 2 provides a simple graphical guide to identifying the source of spurs from the different mismatches in an interleaved ADC.

 

 

Figure 2 Interrelationship of staggered mismatch

The spur caused by the offset mismatch is isolated at fS/2. It is relatively easy to locate and identify. If we only look at the gain mismatch, it is a low frequency (or DC) type of mismatch. The gain component of the bandwidth mismatch can be separated from the gain mismatch by performing a low frequency gain measurement near DC and then performing a gain measurement at a higher frequency. The gain mismatch is not a function of frequency, while the gain component of the bandwidth mismatch is a function of frequency.

A similar approach can be taken for timing mismatch. Perform a low frequency measurement near DC and then perform a subsequent measurement at a higher frequency to separate the timing component of the bandwidth mismatch from the timing mismatch.

Keywords:ADC Reference address:Bandwidth Mismatch Between Interleaved ADCs

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