A single-cycle control scheme and application based on bridgeless APFC circuit

introduction

With the development of power electronics technology, nonlinear loads such as rectifiers and switching power supplies in the power grid are increasing. These power-consuming devices with impact will cause serious distortion of the input current on the grid side, generate a lot of harmonic pollution, and cause the power factor of the grid to be too low, so it is imperative to improve the power factor.

In the early days, power factor correction was achieved by adding filter inductors and capacitors after the rectifier, and the power factor was generally only about 0.6. In the 1990s, active power factor correction (APFC) was created, which is to connect a DC/DC switching converter between the rectifier and the load. Its basic principle is to force the AC input current waveform to track the AC input voltage waveform through a control circuit, thereby realizing the sinusoidalization of the AC current waveform and synchronizing it with the AC input voltage waveform. The power factor can be increased to above 0.99.

APFC Circuit Topology

1. Traditional APFC topology with bridge

The traditional Boost  APFC circuit consists of a rectifier bridge and PFC, as shown in Figure 1. When working, there are three semiconductors working in the flow path, and the power factor is low. When the converter power and switching frequency increase, the system conduction loss increases significantly, the overall efficiency is low, and the control circuit is more complicated.

2. Basic bridgeless APFC topology

In view of the problems of traditional bridge circuits, this paper proposes a bridgeless circuit that can improve PF and reduce conduction loss, as shown in Figure 2. Table 1 compares the bridge topology and the bridgeless topology.

As shown in Table 1, when the MOSFET is turned on and off, the bridgeless APFC saves a diode compared to the bridge APFC. After theoretical calculation, it is concluded that the bridgeless APFC can improve the efficiency by about 1% at full power input. Moreover, the bridgeless topology is more conducive to circuit integration. However, the basic bridgeless Boost APFC circuit has the problems of severe common-mode interference and difficult current sampling.

3. Dual diode bridgeless APFC topology

In order to solve the problems of severe EMI and difficult current sampling in the basic bridgeless Boost APFC circuit, the basic bridgeless Boost APFC circuit is improved. As shown in FIG3 , two fast recovery diodes VD3 and VD4 are added to the basic bridgeless Boost APFC circuit.

In Figure 3, the resistor Rs is the current detection resistor in the inductor, which simplifies the current detection circuit. Although Rs will produce a certain loss during operation, as long as the resistance value is selected appropriately, the loss of the detection resistor accounts for a very small percentage of the total power loss. In this way, the AC and DC sides share the same ground, achieving the purpose of suppressing common-mode interference. 4. Working principle of dual-diode bridgeless topology The working process of the dual-diode bridgeless circuit is as follows:

(1) When the power supply voltage is in the positive half cycle, as shown in Figure 4, the thick black line in Figure 4 shows the current path during the positive half cycle of the input voltage.

Mode 1: Diodes VD1 and VD2 are reverse biased and cut off. The control switch VT1 is turned on, and the input current returns from the positive electrode of the power supply through L1, VT1, and VD4 to the negative electrode of the power supply to form a current path, storing energy in the inductor L1. The load is provided with energy by the energy storage capacitor C.

Mode 2: When the switch VT1 is turned off, the induced electromotive force generated when the inductor current suddenly changes makes the diode VD1 forward biased and the current forms a loop through the inductor L1, VD1, and VD3. At this time, the inductor releases energy, and the capacitor C and the load RL are powered by the inductor and the power supply in series.

(2) The operating mode of the negative half cycle of the power supply voltage is shown in Figure 5. The thick black line in Figure 5 shows the current path during the negative half cycle of the input voltage.

Mode 3: VD1 and VD2 are cut off. The control switch VT2 is turned on, and the input current returns from the positive pole of the power supply through L2, VT2, and VD3 to the negative pole of the power supply to form a current path, storing energy in the inductor L2. The load is provided with energy by the energy storage capacitor C.

Mode 4: Switch VT2 is turned off, VD2 is turned on, and the current forms a loop through inductor L2, VD2, and VD4. At this time, the inductor releases energy, and the capacitor C and the load RL are powered by the inductor and the power supply in series. APFC control scheme

There are three traditional control schemes for power factor correction, namely peak current control, hysteresis current control, and average current control. However, the traditional control scheme must be based on the multiplier, which makes the control circuit complex.

This paper adopts a new control method that does not require a multiplier - single-cycle control.

The biggest feature of single-cycle control is that by controlling the duty cycle of the switch, the average value of the controlled quantity can be exactly equal to or proportional to the given VREF regardless of whether the circuit is in a steady state or a transient state, thereby effectively suppressing the disturbance on the power supply side within one cycle. Single-cycle control technology does not require error synthesis in the control loop, and has the advantages of fast system response, constant switching frequency, small current distortion, and easy implementation. It is widely used in new control technologies of APFC circuits.

IR1150 is a CCM control chip that uses IR's unique single-cycle control technology to provide a low-cost, simple-to-design solution for APFC circuits. The chip is mainly composed of a voltage error amplifier, a current detection amplifier, a reset integrator, a PWM comparator, and an RS trigger, as well as a 7 V reference voltage and some protection circuits. The core circuit is an integrator resetter, as shown in Figure 6.

Its control loop includes a current inner loop and a voltage outer loop. The current loop uses an embedded input voltage signal and adjusts the duty cycle related to the input voltage through pulse width modulation, so that the input average current follows the input voltage and is a sine wave. As long as the circuit works in continuous mode, this tracking relationship can be maintained. The single-cycle working waveform is shown in Figure 7.

Bridgeless APFC Circuit Simulation

1. Simulation circuit

This paper uses the modules in the SimPowersystems module set in MATLAB Simulink to build a bridgeless active power factor correction simulation circuit, as shown in Figure 8.

Simulation parameter design: input AC voltage 15 V, 50 Hz; output direct As shown in Figure 8, the dotted box is the main circuit of the dual-diode bridgeless APFC. Among them: ui is the input AC 15 V power supply, VD1~VD4 are fast recovery diodes, VT1, VT2 are switch tubes. L1, L2 are boost inductors, Cout is the output capacitor, RL is the DC load, R1, R2, R3 are output voltage sampling resistors, Rs is the input current detection resistor, and Subsystem1 is the power factor measurement subsystem. Oscilloscope u/i, oscilloscope i, oscilloscope uo, and oscilloscope PF are used to measure the input AC voltage and current, input AC current, output DC voltage, and system power factor respectively.

The solid-line frame in Figure 8 is a single-cycle control drive circuit. Its control principle is that the modulation voltage Vm is obtained by comparing the feedback voltage obtained by the main circuit output voltage through the voltage divider resistor R3 with the 7 V reference voltage VREF, and is divided into two paths:

Vm and the current detection signal Iin Rs are calculated to obtain Vm - Iin Rs; the integrator integrates the modulation voltage Vm to obtain the triangular wave ∫Vm dt.

When the pulse comes, the integrator works, and then compares the above two signals. When Vm - Iin Rs >∫Vm dt, the comparator output is 1, driving the switch tube to turn on; when Vm - Iin Rs <∫Vm dt, the comparator output is 0, and the switch tube is turned off. 2. Simulation results

Figure 9(a) shows the input current waveform, which is basically a sine wave after the circuit stabilizes. Figure 9(b) is a partial zoom of the input current in the simulation time of 0.102~0.103 s, which clearly shows that the input current can track the input voltage in time to achieve the purpose of power correction.

This paper proposes a single-cycle control scheme based on a bridgeless APFC circuit. The single-cycle controlled bridgeless APFC used in this scheme uses fewer switching devices in the main circuit, has high circuit efficiency, and is conducive to circuit integration; and the control scheme of this paper no longer requires a multiplier, which is simple and easy to implement. From the simulation results, this scheme achieves the purpose of power factor correction.