Design of a parallel device based on a self-current balancing inverter without master and slave

1 Introduction

Inverter parallel operation is an effective way to improve system reliability and expand system capacity, and is widely used in uninterruptible power supplies. The modularity, easy expansion, high reliability and high power of inverter parallel systems are the development trends of future research.

The non-master-slave self-current-sharing module inverters designed here only need to detect the voltage, current and grid power voltage phase and frequency of each output to achieve the synchronization of the output voltage and power sharing control of each module. There is no master-slave distinction between modules, and signal exchange is transmitted through the CAN bus, so that the interference signal can be received as little as possible, improving the reliability of the system. The device uses DSP for main control and FPGA for auxiliary control. The system responds quickly, and hot-swapping between inverters does not affect the stable operation of the other online inverters, thereby achieving the purpose of stable operation and automatic current sharing of non-master-slave inverters in parallel.

2 Inverter parallel current sharing strategy

2.1 Main circuit topology

The topology of the non-master- slave self-current -balanced inverter parallel system designed here is shown in Figure 1. The main circuit consists of two full-bridge circuits. The first full-bridge H1 performs unity power factor rectification AC/DC on the grid, which has less pollution to the grid; the second full-bridge H2 performs DC/AC parallel output voltage control to supply power to the load, and ensures that each parallel inverter shares the load evenly and there is no circulating current between them. Ls is the power frequency inductor on the grid side, and Cs is the capacitor on the grid input side. The DC filter capacitor C constitutes the support link of the DC voltage. The load end uses T-type filters Lo, Co, and L1, and the system supplies power to the load in parallel.

2.2 Current Sharing Strategy Analysis

Figure 2 shows an equivalent model of two inverters in parallel, and multiple inverter models are similar thereto, wherein u1 and u2 are no -load voltages of inverters 1 and 2, i1 and i2 are output currents of inverters 1 and 2, and Z1 and Z2 are equivalent output impedances of inverters 1 and 2, which can generally be approximately equivalent to reactances, i.e., Z1=Z2=jX, uo, io, and Zo are the load voltage, load current, and load impedance of the parallel bus, respectively, and the phase differences between u1, u2 and uo are φ1 and φ2, respectively, i.e., u1=U1∠φ1, u2=U2∠φ2, and uo=Uo∠0°.

According to Figure 2 and the above analysis, the inverter output current is:

From the above power analysis, it can be seen that the output active power of the parallel inverter is approximately only related to the voltage phase, and the output reactive power is approximately only related to the voltage amplitude. 2.3 Parallel system control strategy

When the inverters are operated in parallel, H2 works in the sinusoidal pulse width modulation (SPWM) inversion mode. Each inverter first measures its own output voltage ui and its own output current ii, calculates the active power Pi and reactive power Qi output by the module, and transmits them to other modules. This module makes a difference between its own active and reactive values ​​and the average power Paver=∑(P1+P2+ …+Pn)/n and Qaver=∑(Q1+Q2+…+Qn)/n obtained by statistics of other modules in the parallel system, and obtains the frequency adjustment amount △fi and amplitude adjustment amount △Umi of the i-th inverter output voltage reference wave after system PI adjustment. In addition, the frequency of each inverter output voltage ui adopts the method of tracking the frequency of the grid voltage us, and detects in real time whether the phase difference and amplitude difference between ui and us meet the parallel conditions. The control strategy block diagram is shown in Figure 3.

As shown in Figure 3, the parallel system achieves output voltage difference by controlling the output power of each inverter to be equal, thus meeting the inverter parallel conditions. Each inverter exchanges its active and reactive signals output to the load through the CAN bus. Each inverter uses the average power as the power reference value, and adjusts the error through the PI controller to adjust the reference value of the voltage frequency and amplitude, that is, adding two power control loops on the basis of the original voltage instantaneous value inner loop and effective value outer loop.

The system automatically detects the number of working inverters and quickly calculates the average power. It can respond quickly when a unit is suddenly added or removed from the system, ensuring that the system continues to operate stably and realizing the system hot-swap function.

2.4 Power calculation

When using DSP for digital control, it is impossible to directly perform integral operations in the continuous domain. In order to quickly and accurately calculate the active and reactive power, the design here uses the full-wave Fourier transform method to orthogonally extract power calculation in the digital domain. Assume that the number of DSP sampling in a fundamental frequency sinusoidal cycle is N, u(k), i(k) are the output voltage and current, sin(k), cos(k) are orthogonal fundamental frequency waves, then the power calculation can be rewritten as an accumulation operation in the discrete domain:

In the digital domain, k is used to record the sampling number. When a fundamental wave cycle starts, k is reset to zero. When a fundamental wave cycle k=N-1 is completed, it is reset to zero again. DSP divides a fundamental wave cycle (2π) into N equal parts, calculates the sine and cosine values ​​of each equal part, and generates a sine and cosine table. The sine and cosine values ​​can be read by table lookup for calculation. After each sampling, the above calculation method is used to calculate the active power and reactive power within a fundamental wave cycle. 3 Experimental Analysis

3.1 Main system parameters

In order to verify the effectiveness of the master-slave-free self -current-balanced inverter parallel device and control strategy designed here , an experimental prototype was built. The prototype main controller uses TMS320F2812, and the auxiliary controller uses XC2S200-5PO FPGA. The DSP completes the main control function, and the FPGA completes the pulse generation, I/O port buffering, system protection and other functions. The switch tube uses PM150CLIA120 IPM, and the human-machine control interface uses MT6070iH. The main parameters of the system are: grid side inductance Ls=3mH, grid side capacitance Cs=40μF, DC side capacitance C=2 200μF, output side inductance Lo=3 mH, output side capacitance Co=40μF, parallel side inductance L1=2 mH, DC side voltage Udc=400 V, switching frequency 10kHz.

3.2 Steady-state experimental analysis

The front-stage full bridge H1 of the system can perform unity power factor rectification, which has less pollution to the power grid. Figure 4a shows the waveforms of the grid voltage us and current is on the rectifier side. Udc is the voltage of C, and Idc is the DC current after rectification. It can be seen that us and is are in phase, the power factor is high, and the fluctuations of Udc and Idc are small. The system performance meets the design requirements. The system is operated under linear load. Figures 4b and c show the load and circulating current waveforms when the three prototypes are operated in parallel. As shown in Figure 4b, the effective value of the load voltage can be stabilized at 220V, THD=1.6%, and has a high power factor. As shown in Figure 4c, the three inverters can evenly share the load power, and the circulating current between the inverters is less than 2A, and the parallel operation is stable.

3.3 Transient experimental analysis

Figure 5 shows the transient experimental waveform of the parallel system being able to automatically achieve current sharing after a sudden increase or decrease of an inverter when the system is in parallel operation . At this time, active power, reactive power control and parallel voltage control can ensure the stable operation of the system.

As shown in Figure 5, the sudden increase or decrease of an inverter does not affect the stable operation of the system. The load voltage and current also remain basically stable. After a short adjustment, they can quickly achieve parallel operation and still evenly distribute the system power.

According to the above analysis, the experimental results are consistent with the theoretical analysis. The parallel system can work normally in both steady state and transient state and meets the control requirements, which proves the correctness and feasibility of the master-slave-free self- current balancing inverter parallel device designed here.

4 Conclusion

A device that supports hot-swap automatic current sharing without parallel connection of master-slave inverters is designed . According to the relationship between active and reactive power and amplitude and phase, the circulating current is reduced to achieve load power sharing, and the stability of the system operation is verified by inverter parallel connection experiment.