AD834 for DC to 500MHz Applications

Introduction

The AD834 is the fastest four-quadrant multiplier available, with a usable bandwidth of 800 MHz, compared to 60 MHz for the two-quadrant AD539, 10 MHz for the four-quadrant AD734, and 1 MHz for the four-quadrant AD534. The monolithic construction and high speed make the AD834 ideal for high-frequency applications such as balanced modulation and demodulation, power measurement, gain control, and video switching, which have long been beyond the range of analog multipliers. The

AD834 does not sacrifice accuracy for speed. Like all ADI multipliers, the device uses laser trimming during the manufacturing process to perform zero calibration of input and output offsets to establish precise scaling. In typical applications, the total static error can be maintained below ±0.5%.

It is available in 8-pin plastic DIP, SOIC, and ceramic packages in commercial, industrial, and military temperature ranges, and operates from ±5 V supplies.

The main challenge of using the AD834 is its current-mode output stage. To maintain the highest possible bandwidth, the AD834 output is in the form of a differential current pair with open collectors. This is inconvenient when a more traditional ground referenced voltage output is required. Therefore, this application note discusses methods for accurately converting the above currents to a single-ended ground referenced voltage.

These applications include wideband mean square detectors, rms-to-dc converters, dual wideband voltage controlled amplifiers, high speed video switches, and transformer coupled output circuits. In many cases, these applications provide the user with a complete and proven solution, including recommended voltage sources for key components.

AD834 Overview The

AD834 is the result of Analog Devices' continued pursuit of high precision analog signal processing, and Figure 1 provides its schematic in block diagram form. Specifically, it incorporates ADI's two decades of valuable experience in manufacturing analog multipliers. The device is constructed using a 3 GHz epitaxial bipolar transistor process using laser trimmed thin film resistors. Due to the special attention to detail, distortion and noise are exceptionally low. Figure 2 shows a more detailed simplified circuit schematic.

Figure 1. AD834 block diagram

The X and Y inputs are applied to a high speed voltage-to-current (V/I) converter with a 285 Ω transimpedance and approximately 25 kΩ small signal input resistance. The full-scale input voltage at both inputs is ±1 V. The input bias current is typically 45 A. Therefore, the dc resistance at both inputs of the differential pair must be equal to minimize offset voltage, just as with an op amp. The input resistance also minimizes the risk of high frequency oscillations. The common-mode range of the V/I converter is ±1.2 V with the recommended supply voltages. Over this range, the differential inputs exhibit 70 dB of common-mode rejection, which is conservatively rated for ranges < 100 kHz. Even-order distortion within the V/I converter is inherently low, while built-in distortion cancellation circuitry reduces odd-order nonlinearity to typically ±0.05%.

Figure 2. Simplified AD834 schematic.

The multiplier core is a familiar translinear circuit. The translinear principle [Ref. 1] exploits the precise logarithmic relationship between the base-emitter voltage (VBE) and the collector current (Ic) of a bipolar transistor. The input and output signals of a translinear circuit are always in the form of currents. The voltage swings at the internal nodes are small, so there is no need to charge and discharge parasitic junction capacitances, which are a common cause of reduced bandwidth and limited slew rate. As a result, translinear multiplier cells are inherently fast; they are also easy to implement in a single-chip form. However, these devices can introduce distortion if not carefully designed.

This distortion is primarily due to the mismatch of the emitter regions and the resistance (ohms) within the core transistors (Ref. 2). Following the traditional convention of channel naming, as shown in Figure 2, the X channel is susceptible to the above effects, while the Y signal path remains essentially linear (the four output devices Q3 to Q6 are in many ways similar to a common-base stage or cascode circuit). Therefore, signals that require the lowest possible distortion should always be processed by the Y channel. For example, in a balanced modulator application, the carrier (local oscillator voltage) should be applied to the X input and the baseband signal to the Y input.

The core outputs are in the form of differential current pairs. Today, the scaling of these currents is typically controlled by adjusting the bias current in a V/I converter at the X input, which also determines the current in the diode-connected transistors (Q1 and Q2).

In a classic voltage output multiplier, the adjustment range required to absorb the inevitable resistor mismatch is small, and this method of adjusting the scale factor is acceptable. But in the AD834, the transfer function involves two input voltages, VX and VY, a scaling voltage (generated in the bandgap reference circuit and trimmed to a precise value, here assumed to be 1 V), and an output current, lW:

In this expression, the resistor value R determines the calibration of the output current. During manufacturing, the initial uncertainty of thin film resistors can be as high as ±20%, and the conventional method of adjusting the scale factor results in other trade-offs (such as loss of usable signal range in the X-input V/I converter).

Therefore, the AD834 uses a "Gilbert gain cell" [Ref. 3] after the core to provide the required adjustment of the effective value of R, which is actually achieved by adjusting the current IG, thereby changing the current gain of the cell. After IG adjustment, R has an effective value of 250 Ω, which produces a full-scale output current of ±4 mA when both inputs are at full-scale values ​​of ±1 V. The typical current gain is 1.6, and because this type of amplifier is very fast and buffers the core output, the overall bandwidth of the multiplier is actually better than using the core output directly.

The bias current from the core and the gain setting current IG produce a large regulated current (typically 8.5 mA) that flows into outputs W1 and W2 (pins 4 and 5). Only the differential output is accurately specified to ±4 mA.

The output current can be converted back to a voltage in a variety of ways. In the simplest case, load resistors connected to the positive supply may be used, but these resistors do not convert the (two) differential outputs to a single-ended voltage.

For the AD834 to operate properly, the output pins (4 and 5) must be pulled above V+ to avoid saturation of Q7 to Q10. To avoid the hassle of separate supplies, several circuits included here use a dropping resistor in series with the AD834 positive supply pin (6); a value higher than required for decoupling.

This dropping resistor reduces the voltage at pin 6, providing additional bias margin for the output transistor. For example, in the mean square circuit shown in Figure 3, 11 mA of quiescent current across the 169 Ω dropping resistor produces 1.86 V of headroom. Since the purpose is only to decouple the power supply, the decoupling resistor connected in series with the negative supply at pin 3 is only 10 Ω.

Figure 3. DC to 500 MHz RMS circuit.

Most of this application note is concerned with more efficient ways of loading the outputs. For example, because they are fully calibrated, the outputs of two or more AD834s can be accurately summed by connecting them in parallel, as in the rms application discussed later in this application note.

Mean square detector

First, let's discuss the mean-square detector (Figure 3), whose output is a dc voltage proportional to the input power. Requiring only a calibrated signal generator and a dc voltmeter, this circuit illustrates the AD834's ultrahigh speed capabilities and is therefore very useful.

The input signal is applied to the X and Y inputs connected in parallel. The instantaneous output current is therefore proportional to the square of the input voltage. The square of a sinusoidal input voltage of amplitude A is the cosine of the offset at twice the frequency:

If the input to the AD834 has the sinusoidal form described above, the instantaneous output current (using Equation 1) is:

For a sinusoid with a maximum amplitude of 1 V, this averages out to only 2 mA.

The full-scale differential voltage measured across Pins 4 and 5 of the AD834 is therefore 2 mA × (50 Ω + 50 Ω), or 200 mV. This average is extracted by a low-pass filter consisting of a 4.7uF 0.022 F (AVX part #SR505E475MMAA and #SR505a223JAA) capacitor in conjunction with a 50 Ω collector load resistor having a -3 dB frequency of approximately 650 Hz.

Since the 4.7uF capacitor uses a compact but lossy Z5U dielectric material, while the 22uF capacitor uses a high Q NPO dielectric that ensures good filtering even at the highest frequencies, the two capacitors are connected in parallel. Note that the 4.7uF capacitor has a tolerance of -20% to +80%, so its -3 dB frequency is not precise, but it is usually not necessary for the device to have precise characteristics. Further filtering is performed by the capacitor shunted from the feedback resistor of the AD711 op amp, which is configured to have a -3 dB frequency of 65 Hz.

Due to finite averaging by the circuit, some ripple will occur at low frequency inputs.

For the circuit shown, a 1 kHz input will produce the mean square value plus -42 dB 2 kHz ripple; for a 100 kHz input, the ripple is only -80 dB. Because the output bandwidth is limited, a general-purpose, low-speed op amp with ample common-mode range can be used, eliminating the need for level shifting. The amplifier differential gain can be appropriately chosen to provide a convenient scaling factor.

The full-scale gain for the circuit shown in Figure 3 is calculated as follows. The average output current for a 1 V (peak) sinusoidal input is ±2 mA, producing ±100 mV across each 50 Ω output load resistor, or 200 mV differential. The amplifier is configured for a differential gain of 2.5 (feedback resistance to source resistance), resulting in a circuit gain of 0.5 V dc output for a 1 V rms input.

The bandwidth of this circuit is limited by the package capacitance and inductance. In an 8-lead cerdip package, the multiplier response typically starts rising at 500 MHz, peaks at 800 MHz, and then rolls off due to package resonance. The 24.9 Ω resistor at the input dampens the resonance, producing a response that is essentially flat before 800 MHz. (The package inductance of the surface-mount AD834 is different.) Figure 4 shows the results for three different power levels over the entire frequency range, using the test configuration shown in Figure 5.

Ignoring the 24.9 Ω resistor in series with the high impedance input, the input resistance of the mean square circuit shown in Figure 3 is 50 Ω. Since the full-scale input range is ±1 V, the maximum measurable power into a 50 Ω input load is 10 mW (20 dBm) assuming a sinusoidal input.

Figure 4. Frequency response of the mean square circuit at -5 dBm, 0 dBm, and +5 dBm input power levels.

Figure 5. Test configuration

To achieve a larger input range, a voltage divider with a 50Ω series resistor at the input will reduce the voltage across the AD834 while maintaining the proper termination resistance. For example, if the input signal is applied to a 45Ω resistor in series with a 5Ω resistor to ground, tapping the AD834 input at the mid-node of the voltage divider will provide 20 dB attenuation to the input signal while maintaining a 50Ω (45Ω + 5Ω) termination resistance.

The detection of low power signals is limited by the dc offset and common-mode rejection of the op amp. For example, a -20 dBm signal corresponding to 22.4 mV rms across 50 Ω will produce a 4.5% error when there is only 1 mV offset in the op amp. If the AD834 X-channel offset is only 2 mV, this will produce a 10% error.

The rms-to-dc converter

rms circuit (Figure 6) is not simply adding a square root circuit after the rms detector circuit described above. The frequency response is determined by the front-end squarer and the output filter. According to the rms specification, the squarer is active after 500 MHz, and the lower -3 dB frequency response is 340 Hz (100Ω and 4.7iF). Note that the resistor divider network at the input determines the full-scale input voltage to be ±2 V peak.
 

The square root function is performed by squaring the AD834 within the feedback loop of the AD711 op amp. The 2N3904 transistor acts as a buffer. The resistor divider network (two 100Ω) between the AD834 buffer output and the X and Y channel inputs for the square root portion determines that the output is adjusted to ±2 V full scale.
 

The current difference of the two AD834 outputs is taken. Accurate output difference and summing can be achieved due to the high accuracy of the laser trimmed AD834 output signal current scaling. The AD711 forces the difference between the two AD834 signal currents to zero. Any error in the zero calibration will produce a voltage across the two 100Ω pull-up resistors.

After additional filtering and level shifting through the 15 kΩ, 85 kΩ, and 0.1uF network, the residual error is amplified by the overall AD711 open-loop gain. The amplified error signal forces the output of the AD834 within the feedback loop to match the output of the mean square AD834. The error is zeroed when the rms circuit output is equal to the square root of the circuit input mean square function and the rms function.

The accuracy of the circuit at small signal levels is limited by the inevitable offset voltage. Although a nominal 0 V input (1 mV error) to the mean square function produces a 1 uV output error, the same input error can produce a 31.6 mV output error through the square root circuit.

Figure 6. DC to 500 MHz RMS-to-DC Converter

DC-Coupled VCA Applications

If the dc response of the AD834 cannot be eliminated, some form of passive or active level shifting must be used because the common-mode range of high speed op amps is often insufficient. The following applications show the use of active or passive level shifting circuits in wideband voltage controlled amplifier solutions.

DC to 60 MHz Voltage Controlled Amplifier Using Passive Level Shifting Figure 7 shows a schematic of a circuit using a passive network as a level shifter.

The op amp chosen here is the AD5539.

Figure 7. DC to 60 MHz voltage controlled amplifier using passive level shifting
 

The AD5539 is built on the same process as the AD834 and provides a gain-bandwidth product of 2 GHz at high closed-loop gain. Unlike most op amps, the AD5539 has a ground pin and an all-NPN output stage that operates in "Class A" to achieve the device's high speed (see Figure 8). A closer look reveals that there is limited "headroom" between the output node and the inputs, and between these voltages and ground. The high speed and other unconventional properties of the AD5539 require special care when used.

Figure 8. ADS539 operational amplifier schematic
 

First consider the consequences of a Class A output stage. In most op amps, the output can be either "pulled up" or "pulled down" across the load, but the NPN emitter-follower output stage can only pull up. The AD5539 has an internal pull-down resistor (R11) of 2 kΩ, which can only supply 2 or 3 mA. A general-purpose high-speed multiplier must be able to swing at least ±1 V while driving a minimum load resistance of 50 Ω. At this output level, the load current is ±20 mA, so it must be supplied through an external pull-down resistor. In practice, the pull-down current must be much greater than this value and requires careful consideration.

Figure 9 shows the calculation method. The 425 mV voltage source is the "IBRC", which is the AD834's stable current of 8.5 mA multiplied by the load resistor RC, which is set to 50 Ω here. When the full-scale output current is +4 mA, the 200 mV source in Figure 9(a) is the "IWRC" generator. From this, V1 - 5.375 V and V2 - 5.775 V are calculated.

Next, the voltage at W2 is calculated. Since the input current to an ideal op amp is zero, there is no load on W2 and the voltage is V2 times the attenuation ratio of 125/(125 + 50), or 4.125 V. Since the input voltage to an ideal op amp is zero and W1 is at the same voltage, we can now calculate that the current in the upper 50 Ω resistor is (5.375-4.125)/50 mA, or 25 mA. Again, there is essentially no current flowing into the op amp inputs, so all of the 25 mA flows into the 125 Ω feedback resistor, creating a 3.125 V drop across it. Finally, this voltage drop is subtracted from the voltage at W1 (4.125 V) to calculate the output as +1 V.

Note that the result is somewhat surprising at this point: although 20 mA flows into the load, a larger current of 25 mA flows into the feedback resistor! This unusual state of affairs is due to the extremely low value of the feedback resistor required to reduce the scale factor to the expected value, and the relatively large voltage required at the output of the AD834 to ensure proper biasing of outputs W1 and W2. Therefore, even though the load only needs to source 20 mA, at least 5 mA still needs to be provided in the pull-down resistor RP to bias the output emitter-follower in the AD5539. The situation becomes more serious when the output current of the AD834 reverses, because now a 20 mA current needs to be sunk in the 50 Ω load, and the voltage across the feedback resistor is even higher.

This situation is shown in Figure 9(b). The calculation process is the same as before, and we find that the current in the feedback resistor is now 39.7 mA. Therefore, RP needs to provide 20 mA of load current and another approximately 40 mA in the feedback path, while the voltage across it is 5 V. This requires RP = 83Ω. In practice, this value should be slightly lower to prevent the slew rate from limiting the fall time. In addition, the feedback resistor will be increased from 125Ω to 133Ω to compensate for the limited gain of the AD5539 under the above heavy load conditions. If we find the parallel sum of the 50Ω load, the 70Ω pull-down resistor, and the effective feedback resistor of about 150Ω, the actual load on the amplifier is only 24 Ω!

The AD5539 is stable at uncompensated gains greater than 5, and the AD5539 in this circuit is operated at a gain slightly greater than 3. The 0.01uF and 10Ω network performs compensation by giving up enough open-loop gain to achieve stable performance when driving a 50Ω load. For higher impedance loads, the 10Ω compensation resistor may need to be reduced.

Figure 9. Equivalent circuit for calculating pull-down resistor values.

Between nodes W1 and W2 is a level-shifting network with an average voltage of approximately +4 V connected to the AD5539 inputs, which are close to ground. With the values ​​shown, the op amp inputs are set slightly below ground (approximately -460 mV). This network halves the low-frequency open-loop gain, which has some effect on dc accuracy when an offset voltage is present at the AD5539 inputs. If output offset is important, a 500 Ω potentiometer in series with the 3.74 kΩ resistor should be inserted and the slider set to -6 V.

Next, set the X and Y inputs to zero and adjust for zero output.

Also note that the "internal" pins X1 and Y2 on the AD834 should be grounded to minimize high frequency feedthrough; the resulting phase inversion at the X input is corrected by switching W1 and W2.

Figure 10 shows the pulse response when an input pulse is applied to the X input and the Y input is set to +1 V, indicating a rise time of 6 ms.

Figure 10. Pulse Response of a DC to 60 MHz Voltage Controlled Amplifier

Figure 11 shows a set of frequency responses taken from an HP8753B network analyzer for +1 V, 316 mV, +100 mV, and 0 V Y inputs. At 0 V, the Y input was adjusted to zero the input offset. Note that the high frequency feedthrough is less than -65 dB of full scale (f < 3 MHz).

Figure 11. Frequency response of a voltage-controlled amplifier from DC to 60 MHz.

DC to 480 MHz voltage controlled amplifier using active level shifting.

Figure 12(a) shows an active level shifter using a PNP transistor as a common-base stage or cascode circuit. Here, the AD834 is simulated by three ideal current sources, two for 8.5 mA bias current and one for ±4 mA differential signal current. The transistor base is connected to +5V, and in the absence of a signal, the emitter potential remains at 5.7 V, producing a voltage of 3.3 V across resistors R1 and R2. Figure 12(b) shows an equivalent circuit.

Figure 12. AD834 output stage using active level shifters.

Solving for the current flowing into the emitter when the signal current generator is zero yields an equivalent DC bias current of 7.17 mA. In the AC domain, for the signal current generator, both R1 and R2 are connected to low impedance nodes. By inspection, the original signal current has been scaled by the following ratio:

Since the output of AD834 has a very high output impedance, the equivalent series resistance can be ignored. Assuming normal, the 7.17mA flowing into the emitter of the cascode circuit across R3 will all flow out of the collector of the cascode circuit. The voltage across R3 is:

The op amp input is 350 mV below ground and within the common-mode range of the wideband amplifier.

The bandwidth of a transistor configured as a cascode circuit is the transistor unity gain frequency (fT), as long as the user does not create any stray poles. When selecting R1 and R2, if their parallel sum is too large for the transistor parasitic emitter-base capacitance, or R3 is too large for the transistor parasitic collector-base capacitance, an interfering pole will be created that degrades the circuit's frequency response.

Figure 13. DC to 480 MHz voltage-controlled amplifier using active level shifting.

Another potential disadvantage when using active PNP level translators is oscillation at the emitter of the cascode circuit. The input impedance of the bipolar junction transistor emitter is inductive at frequencies close to its gain-bandwidth product (fT), while the AD834 output is capacitive. Due to the high bandwidth of the system, these impedances can cause oscillation.

To prevent such oscillations, the emitter in Figure 12 is isolated from the AD834 output using R2. This prevents oscillations while providing the signal attenuation (gain control) described in Equation 4. The 2N3906 provides wideband level shifting without resonance or oscillation. Extra care must be taken when using other transistors.

The signal current at the collector of the cascode circuit is now fed as a differential current into the wideband amplifier, forming the voltage converter configuration shown in Figure 13. This configuration is similar to the current-to-voltage converter driven by an op amp that typically follows a current-output multiplying digital-to-analog converter.

The AD9617 is an excellent choice for driving the current-to-voltage converter. The AD9617 is a second generation transconductance amplifier (also called current feedback and TZ amplifier) ​​with a fully complementary output stage (unlike the AD5539) optimized for a 400 Ω feedback resistor.

The AD9617 inputs are connected directly to the collectors of the cascode circuit. The op amp creates a virtual short between the input nodes, forcing all signal current to flow into the feedback path. The converter differential transimpedance is 400 Ω. The required scaling is achieved with the R1 and R2 attenuation network described above. The full-scale gain of the circuit at the output of the AD9617 (X = Y = 1 V) is calculated as:

That is 1.04 V after reversing the termination resistors. The actual circuit shows a full-scale gain closer to unity.

Figure 14 shows the full-scale step response (-1 V to + 1 V) applied to the X input with the Y input set to +1 V, demonstrating that the circuit has a rise time of less than 2 ns and exhibits some overshoot but no ringing. Note that the output swings over 500 V/s.

Figure 15 shows a set of frequency responses taken from an HP8753B network analyzer for +1 V, 316 mV, +100 mV, and 0 V Y inputs. The Y input is actually adjusted to zero the input offset. Note that the circuit has a small signal bandwidth of 500 MHz (at an input power level of 0 dBm). This bandwidth can be achieved with two 1 pF capacitors at the inverting node. High frequency feedthrough is less than -80 dB of full scale (f < 2 MHz).

AD834 used as a video switch

When 0 V and +1 V are applied to the X channel for gate control, and the video signal is applied to the Y channel, the AD834 becomes a high speed video switch. Figure 16 illustrates this concept using a high speed current switch circuit centered around an ECL switch. Current flows through either Q1 or Q2, depending on the input voltage. The current switch ensures clean and fast switching to the determined levels (+1 V and ground), allowing the user to overdrive and underdrive the gate inputs.

The AD834 turns on when the gate circuit input rises from +1 V to +2 V. Below 1 V, Q1 draws nearly all of the current from the 216 Ω resistor; the 2N3906 transistor turns off. In this state, the 100 Ω resistor from the X2 input to ground accurately turns off the Y channel, while the Y channel feeds through to the output measured at -50 dB. With the Q2 base held at 1.6 V, the transistor emitter potential is 2.35 V. With the X2 input independent of the high level of the gate input, the steady 10.2 mA (minus the base current) from the 261 Ω resistor produces a +1 V voltage across the 100 Ω resistor.

Figure 17 shows an oscilloscope photograph of a 200 MHz signal gated with a 1.5 ns rise time pulse. The resulting envelope rise time is 2.7 ns; the fall time is 3.0 ns. Although the switching signal could be slower, the AD834 output stage should have a bandwidth greater than 100 MHz in order to maintain the 3.5 ns envelope rise time.

AC output coupling method

In many applications, the dc component at the output can be discarded. In such cases, a wideband buffer can be easily ac-coupled to the AD834 output. The following circuit shows the use of a simple transformer and balun as a passive, ac-coupled output circuit.

Transformer coupled output

Figure 18 shows the use of a center-tapped output transformer, which provides the necessary DC load conditions at the outputs W1 and W2 and is designed to match the required load impedance by selecting the appropriate turns ratio. The specific choice of transformer design depends entirely on the application. A transformer may also be used on the input side. A center-tapped transformer reduces high frequency distortion and reduces high frequency feedthrough by driving a balanced signal input. Suitable center-tapped transformers include the Coilcra WB2010PC, which is specified by the manufacturer to operate over a frequency range of 0.04 MHz to 250 MHz.

Balun coupled output

Figure 19 shows a circuit that uses DC blocking capacitors to remove DC offsets and a balun (a particularly efficient transformer) to convert a differential (or balanced) signal to a single-ended (or unbalanced) output. The balun consists of a short length of transmission line wound around a toroidal ferrite core and is used to convert a "balanced" output to an "unbalanced" output.
 

Although the same symbols are used as for the transformer, the mode of operation is quite different. Firstly, the load should now be equal to the characteristic impedance of the line, although this condition is not usually important when the line length is short. The collector load resistor RC can also be chosen to reverse terminate the line, but again, this condition only applies when long electrical lines are used.

In most cases, RC should be the maximum value allowed by DC conditions to minimize power loss in the load. The line can be a small coaxial cable or twisted pair.

It is important to note that the upper bandwidth of the balun is determined only by the quality of the transmission line; therefore, it is usually greater than that of the multiplier. This is different from a traditional transformer, where the signal is transferred in flux through the core and is limited by core losses and leakage inductance. The lower bandwidth is generally determined by the series inductance of the line and is also affected by the load resistance (if the DC blocking capacitor C is large enough). In fact, the balun can provide excellent differential-to-single-ended conversion over a bandwidth much wider than that of a transformer.

accomplish

Good high frequency skills are required to build these circuits. The circuit schematic is a suggested layout for a suitable layout. A ground plane is required for all circuits described in this application brief.

The ground plane should cover as much of the component side as possible, but should not be directly under the IC or around any individual pins. Sockets add pin capacitance and inductance and should be avoided. If sockets must be used, use individual pin sockets, such as AMP p/n 6-330808-3. It causes much less stray reactance than molded socket components. On the IC, each power supply trace should be decoupled with a 0.1 F low inductance ceramic capacitor in addition to the main decoupling capacitor. All lead lengths should be kept as short as possible. Leads longer than one inch should use stripline technology.