High Performance Serial Interface Analog Multiplexers ADG731/ADG725

        1 Main features

　　ADG731/ADG725 is a 32-channel/dual 16-channel high-performance monolithic analog multiplexer with a 3-wire control interface launched by ADI. The ADG731 has a 32-to-1 channel conversion function; the ADG725 has two groups of 16-to-1 channel conversion or 16-to-1 differential signal channel conversion functions.

　　The ADG731/ADG725 has a 3-wire interface compatible with SPI, QSPI, MICROWIRE, and some DSP interface standards. After a power-on reset, the circuit's internal conversion registers are zero and all switches are in the open position.

　　The ADG731/ADG725 uses enhanced submicron processing technology to provide low voltage dispersion, which can meet high-speed conversion with low on-resistance and low leakage current. The circuit operates on a single power supply of 1.8V to 5.5V or a dual power supply of 2.5V. The on-resistance is a few ohms (matching the switch resistance) and has good flatness over the full signal range.

　　The ADG731/ADG725 can be used as both a multiplexer and a demultiplexer. The input signal can reach the full supply voltage. When the switch is open, both the signal and the supply voltage are isolated from the output. Before the switch is closed, all channels are disconnected, thus avoiding the formation of a momentary short circuit in the switch channel.

　　The ADG731/ADG725 has the following features:

　　·With 3-wire compatible serial interface;

　　1.8V～5.5V single power supply or 2.5V dual power supply;

　　4Ω on-resistance, 0.5V on-resistance flatness, 42ns switching time;

　　7mm×7mm 48-pin LFCSP package or 48-pin TQFP package;

　　Rail-to-rail operation;

　　Power-on reset;

　　·TTL/CMOS compatible input.

　　2 Pin Functions of ADG731/ADG725

　　The ADG731/ADG725 is available in 48-pin LFCSP and TQFP packages with pinouts.

　　3 Interface Timing and Register Format

　　ADG731/ADG725 is a multiplexer with a 3-wire serial interface (SYNC, SCLK, DIN) and is compatible with SPI, QSPI, MICROWIRE and most DSP interface standards. Data is written into the 8-bit register through the DIN pin under the control of the SYNC and SCLK signals. Figure 2 shows its typical write timing.

　　When SYNC is low, the input conversion register is enabled and an 8-bit register is enabled at the same time. At the falling edge of SCLK, the signal transmitted through the DIN pin will be latched by the conversion register. The bit definition of the input conversion register is given. When SYNC is low and the device receives 8 clock cycles, the switch will automatically update the state and invalidate the input conversion register.

　　The CAS and CSB control bits of the ADG725 allow the user to flexibly select the input state of the converter.

　　The communication channel between ADG731/ADG7-25 and microprocessor (i.e., through 3-wire interface) consists of clock signal (SCLK), data signal (DIN) and synchronization signal (SYNC). At the falling edge of SCLK, ADG731/ADG7-25 must have a group of 8 bits of data valid.

　　4 Typical Application Circuit

　　The ADG725/ADG731 can be used in large, multi-channel optical network systems where higher port counts are required. The ADG725/ADG731 is well suited for optical networks because it can connect multiple channels in a single control circuit without increasing board size.

　　In the optical network control loop circuit, the 0V to 5V output of the AD5532HS is amplified to 0V to 180V and used as an excitation to control and measure the position of the MEMS mapping in the irregular optical switch. The exact position of each mapping can be determined by the sensor. The sensor readout is converted to a 1-channel output and enters the 14-bit ADC (AD7894) after passing through the multiplexer ADG731.

　　The control loop is driven by the ADSP-2191M, a 32-bit DSP with an SPI-compatible SPORT interface. The DSP controls the multiplexer by writing data to the DAC and then reading data from the ADC via a 3-wire serial interface.