Design of a Fully Differential Operational Amplifier in 0.6μm CMOS Process

Operational amplifiers are key parts in data sampling circuits, such as pipeline analog-to-digital converters. In such designs, speed and accuracy are two important factors, and both of these factors are determined by the various performances of the operational amplifier. The

two-stage high-gain operational amplifier with common-mode feedback designed in this paper is divided into two stages. The first stage is a sleeve-type operational amplifier to achieve high gain; the second stage adopts a common source circuit structure to increase the output swing. In addition, common-mode feedback is introduced to improve the common-mode rejection ratio. This scheme can not only meet the requirements of high gain and high common-mode rejection ratio in theory, but also pass the software simulation verification. The results show that the DC gain of the structure can reach 80 dB, the phase margin reaches 80°, and the gain bandwidth is 74 MHz.

1

Operational amplifier structure There are basically three types of operational amplifier structures commonly used, namely simple two-stage operational amplifier, folded common source and common gate, and sleeve common source and common gate. Among them, the two-stage structure has a large output swing, but the frequency characteristics are relatively poor. Miller compensation is generally used, which can reduce the phase margin, so the stability of the circuit will deteriorate; the sleeve-type cascode structure has better frequency characteristics, and because it has only two main branches, the power consumption is relatively small. However, these are at the expense of reducing the input range and output swing. Therefore, in order to alleviate the limitation of the sleeve structure on the input voltage range, this paper proposes the idea of ​​folding operational amplifier structure. The folded structure has a larger input common-mode level range than the sleeve structure, but at the expense of reducing gain and bandwidth, increasing noise and power consumption. Considering that the power consumption of the folded cascode input stage structure is relatively large, this paper selects the sleeve cascode structure as the input stage, and finally selects the two-stage operational amplifier structure with a fully differential structure as shown in Figure 1.

1.1 Main op amp structure The

fully differential operational amplifier circuit has a stronger ability to suppress environmental noise. The sleeve structure has the characteristics of high gain, low power consumption and good frequency characteristics. Therefore, the first stage amplification structure (i.e., M0~M8) adopts the sleeve fully differential amplifier structure as the input stage. The second stage (i.e., M9~M11) is a common source structure to improve the disadvantage of the small output swing of the sleeve structure, and at the same time, the open-loop gain of the operational amplifier is correspondingly improved. However, as the number of stages increases, the zero poles of the circuit will inevitably increase, which requires higher system stability. Therefore, the compensation capacitor C3 must be introduced to compensate for the additional poles so that the phase margin of the circuit can meet the requirements and the performance is stable. In addition, VB1 in Figure 1 is used to provide tail current mirror bias, VB2 and VB3 are used to provide static DC bias for PMOS and NMOS respectively, and these three bias voltages are provided with bias circuits.

By performing small signal analysis on the operational amplifier, the gain AV1 of the first-stage sleeve-type fully differential structure can be calculated, and the formula is:

A v1≈g2[(gm4τ2τ4)·(gm6τ6τs)]

, where gm2, gm4, gm6 represent the transconductance of M2, M4, M6, respectively, and r2, r4, r6, r8 represent the output resistance of M2, M4, M6, M8, respectively. The

single-ended gain AV2 of the second-stage common-source amplifier structure can be calculated using the following formula:

AV2=-gM10r10

, where gM10 and r10 represent the transconductance and output resistance of M10, respectively. Therefore, the open-loop gain Av of the entire Miller compensation operational amplifier can be expressed by the product of the amplification factors of the first and second stages:

Av="A" v1Av2

1.2 Common-mode feedback circuit

Since this design adopts a fully differential structure, in order to stabilize the output common-mode voltage by stabilizing the DC and ensure that the output stage works in the linear region, a common-mode feedback (CMFB) circuit is usually required. There are generally two types of common-mode feedback circuits. One is the continuous time type and the other is the switched capacitor type. This design adopts the switched capacitor structure, and Figure 2 shows the switched capacitor common-mode feedback circuit. Among them, S1~S6 are switches, C1~C4 are common-mode feedback capacitors, Vout+ and Vout- are the output voltages of the operational amplifier, and ψ1 and ψ2 are two-phase non-overlapping clock signals. VCM is the ideal common-mode output voltage, Vb1 is the ideal common-mode bias voltage, and Vb2 is the actual common-mode bias voltage, that is, the control voltage of the current source in the operational amplifier. In practice, the switches of S1~S6 are all realized by NMOS tubes.

1.3 Bias circuit

The bias circuit is mainly used to provide bias voltage for folded cascode amplifier and common-mode feedback. This paper adopts the wide-swing current source bias circuit structure shown in Figure 3. In the cascode input stage, three voltage biases are usually required. In order to make the dynamic range of the input stage larger, the wide-swing current source in Figure 3 is used to generate the three required bias voltages. According to the design requirements of the wide-swing current source, the following relationship must be met during design:


2 Circuit Simulation Results The

circuit can be simulated using the HSPICE circuit simulation tool and the Shanghua 0.6μm CMOS process model parameters. The simulation results show that the open-loop DC gain of the op amp is 80 dB, the phase margin is 80 degrees, and the unit gain bandwidth is 74 MHz. Figure 4 shows its amplitude-frequency and phase-frequency characteristic curves. As shown in Figure 4, the circuit power consumption is 1.9 mW; the differential output range is -2.48 to 2.5 V; and the power supply voltage is 2.5 V.

3 Conclusion

This paper presents a design method for a low voltage fully differential telescopic operational amplifier and simulates the design method. The simulation results show that the design can meet the design requirements of the operational amplifier in a 20 MHz pipeline analog-to-digital converter while ensuring high gain and low power consumption.